here is the question picture
i do not know how to solve it!
thank you~

 

You need to show YOUR best attempt to work YOUR homework.

We can then see where you are going wrong and help YOU figure out how to get back on the right path.

 

You need to show YOUR best attempt to work YOUR homework.

We can then see where you are going wrong and help YOU figure out how to get back on the right path.

ok wait a minute!

 

ok wait a minute!

this is how i try
please give me some advice

 

is this right?
MOD: rotated and lightened your image.

 

How are you going to implement the C'D' signal using only inverters?

 

In general, if you have a 4:1 MUX, then you can use two signals to drive the select lines and if you are only allowed to use inverters beyond that, then you can only have one other signal since you can only put in a 0, a 1, the other signal, or the complement of the other signal into the data inputs of the MUX. So you can only handle three input signals. But that's if you are implementing arbitrary logic.

If you have more than three signals, you may or may not be able to do it. What you want to look for are combinations of choices for the select signals that make it so that you don't need to combine any of the remaining signals for any of the data inputs.

The one that troubles me is the 7 term. It doesn't mate with any of the others.

 

In general, if you have a 4:1 MUX, then you can use two signals to drive the select lines and if you are only allowed to use inverters beyond that, then you can only have one other signal since you can only put in a 0, a 1, the other signal, or the complement of the other signal into the data inputs of the MUX. So you can only handle three input signals. But that's if you are implementing arbitrary logic.

If you have more than three signals, you may or may not be able to do it. What you want to look for are combinations of choices for the select signals that make it so that you don't need to combine any of the remaining signals for any of the data inputs.

The one that troubles me is the 7 term. It doesn't mate with any of the others.

this is my answer'

 

I see two things that jump out at me right off the bat.

You feed D and D' into the AND gate. What does that do for you?

Second, you use an AND gate. Did the problem say, explicitly, "using a 4-1 multiplexer and inverters"?