Hi,

I have been working on oscillators, when I was analyzing an issue I found that the oscillators is generating more frequency than tuned (5.8kHz instead 5kHZ).

This frequency is connected to IN1 / CLK1 of CPLD. Now I want to know, whether this effects the functionality of CPLD but it seems our module is functionally ok.

I have two questions here :
1.how the clock frequency of CPLD is determined, is it based on the required speed we need ??
2.What happens if the frequency exceeds the specified ??

Thanks in advance..

 

Use a frequency counter, what is a Cpld, and do you have a circuit?

 

Standard way of reading frequency of any periodic signal is use an oscilloscope to measure the period (f=1/p),

or to use an electronic frequency counter.

 

the counter is more common than the osciliscope, as well as more accurate and easier to read. the osciliscope is usually used to get a general idea of the frequency and the actual waveform.

 

the clock accuracy will affect the timer functions and step timing of the cpld if higher than speced, the timers will be a bit fast.

 

A CPLD, Complex Programmable Logic Device, is a programmable logic device much like an FPGA in practice, and completely different otherwise. Is is uses a non-volatile configuration.

Your oscillator running faster means your CPLD will have a different operating frequency - any timers, or time-dependent signals that are derived from your clock signal will be off. That may, or may not, be a problem for your design.

The oscillator oscillates where its parameters allow it to. Without offering more details, we can't really yell you why it might be off. It is about how it was designed, it doesn't care about what does you need. Presumably, it was selected because it is the frequency you need.

Likely, your CPLD will be fine up to a few hundred megahertz before you need to check if the deviation will operate the device out of specifications. You can find out in the datasheet.