I have some questions that I am not sure on how to do, please help.

Question:

The capacity of a RAM module is 16K x 8. (i) How many address and data lines does this module have? (ii) How many of these RAM modules are needed to realise a memory module with a capacity of 64K x 16? Explain your answer. (iii) IF the 64K x 16 memory module in (i) starts at 0000H, design a decoder to construct the memory module from the 16K x 8 modules.

I am not sure on how to do find the number of RAM modules for (ii) and therefore, not able to construct the memory map for (iii).

My answer for (i) is 14address lines and 8 data bits.

Thanks for your help.

 

hi,
How many times does 16K go into 64K, and how many times does 8 go into 16.?

E

Draw a simple block diagram if that helps,,, one block = 16K*8

 

hi,
How many times does 16K go into 64K, and how many times does 8 go into 16.?

E

Draw a simple block diagram if that helps,,, one block = 16K*8

I get a total of 8 chips of 16K x 8 RAM but, if I use a 3-8 decoder for the circuit. 14 address is used for the 16K x 8 RAM and 3 address for the input of the decoder, there will be a total of 17 address which exceeds the limit of 16 address of the 64K x 16 RAM.

 

hi,
As you know the Address lines are A0 thru A15, these are common to all the RAM, so consider you have to Chip Select 4 blocks using the 3 to 8 decoder, so you have to decode the higher order address lines to give 4 chip select lines.

Hint:
How many address lines does a 16K RAM require.??

One on the 3-8 inputs could be connected to Zero.

EDIT:
Look at this decoder map.

 

hi,
As you know the Address lines are A0 thru A15, these are common to all the RAM, so consider you have to Chip Select 4 blocks using the 3 to 8 decoder, so you have to decode the higher order address lines to give 4 chip select lines.

Hint:
How many address lines does a 16K RAM require.??

One on the 3-8 inputs could be connected to Zero.

Sorry for asking, but why chip selects 4 blocks when I required 8 chips?

There are 14 address line for a 16K RAM.

 

Sorry for asking, but why chip selects 4 blocks when I required 8 chips?

Because the chips are in pairs to give D0 thru D15 data lines.
So there are 4 pairs, each pair will have its own Select.

Decoding 2 wires gives 4 Selects, if the higher 3 to 8 input is connected Low.

 

Because the chips are in pairs to give D0 thru D15 data lines.
So there are 4 pairs, each pair will have its own Select.

Decoding 2 wires gives 4 Selects, if the higher 3 to 8 input is connected Low.

Sorry for my lack of knowledge, is it means that 2 nos of 16K x 8 bits is equal to 16K x 16 bits (so it means by a pair? when to realise a memory module with a capacity of 16K?)

 

A Pair of 16K by 8 RAMs connected as a parallel pair gives 16K by 16.

Look at this image, tell me if you understand it.

 

Sorry for my lack of knowledge, is it means that 2 nos of 16K x 8 bits is equal to 16K x 16 bits (so it means by a pair? when to realise a memory module with a capacity of 16K?)

But if it is a pair, then when I construct the circuit, I would still have 8 chips? How do I ensure that at each time, there is only 1 chip operating?

 

S

A Pair of 16K by 8 RAMs connected as a parallel pair gives 16K by 16.

Look at this image, tell me if you understand it.

Really sorry, but I don't get how the connection is done. Why all the chips are interconnected and not the pair that is interconnected only?

 

Which part dont you understand, I cannot make it much clearer.

 

But if it is a pair, then when I construct the circuit, I would still have 8 chips? How do I ensure that at each time, there is only 1 chip operating?

You want to access 2 chips at a time (not 1) so that you have 16 data lines (not 8).
After all, the data for the high byte is paired with the low byte; it is not associated with any other byte.
So Select 0 activates the first pair,
Select 1 activates the second pair,
Select 2 activates the third pair,
Select 3 activates the fourth pair.
4 pairs is 8 chips.

 

Which part dont you understand, I cannot make it much clearer.

I don't know if the connection is like this where all the address lines are connected (A0 - A13) and the decoder is (A14,A15), WR all connected.

Really sorry

 

I don't know if the connection is like this where all the address lines are connected (A0 - A13) and the decoder is (A14,A15), WR all connected.

That should work.

 

I don't know if the connection is like this where all the address lines are connected (A0 - A13) and the decoder is (A14,A15), WR all connected

Usually the Data lines to the RAM are used for both Input [ a Write operation] and Output [ a Read operation].
The WRite pin on the RAM chips select Read OR Write.

The a0 to a13 'single' wire is a shorthand way of drawing all the 14 Pins, instead of a wire for every address pin, likewise with the Data lines d0 - d7 is 8 wires Low BYTE and d8 - d13 is the high BYTE 8 wires.

Do you follow OK.?

 

Thanks a lot for your help