Hello,

I have have some IO that operate in different modes with different clocks. For example, GPIO may be driven by CPU at 125MHz or SPI at 250MHz, depending on mode.



When I add the set_input/output_delays and multi-cycles relative to their associated clocks Jasper CDC definitely freaks out. Will Genus also get confused unless I do set_case_analysis with MMMC?

Or is there a simpler way to constrain these dual-use pins that doesn't involve MMMC? I'm in a corporate-dictated synthesis flow that doesn't tolerate the MM part of MMMC well

Thanks, Tom

 

the best way to not get meaningful reply when asking programming question is to not mention platform and use acronyms.
you can fix logic by using literals instead of variables.