hello,
how simple ic are design in which software in few mm size??

 

Hello,

Have a look here for an example:
http://www.staticfreesoft.com/

Bertus

 

i have downloaded how to learn its working??

 

Hello,

Read the manual.

Bertus

 

how engineer work at nano distance in ic?
how hand can do this for example ic size is in few mm....

 

Hello,

They do not do it by hand.
They use software to design the chips and have the chip made in the chip factory.
When you got some spare time, here are some videos on VLSI design:
http://learnerstv.com/Free-Engineering-Video-lectures-ltv066-Page1.htm
http://learnerstv.com/Free-Engineering-Video-lectures-ltv066-Page2.htm
http://learnerstv.com/Free-Engineering-Video-lectures-ltv176-Page1.htm

Bertus

 

Actually, sometimes it is still done by hand. The IC designs we did were almost always over 90% (and sometimes fully 100%) laid out by hand. What made this possible was that our chips were usually array-oriented (imagers, detectors, displays, etc) will very little random logic. So a huge fraction of the time and effort was spent on designing, simulating, and laying out the pixel but then this was arrayed. Our chips were almost always mixed-signal and very sensitive to noise and stray capacitive coupling, so the layouts had to be very carefully considered. It's definitely a specialty niche -- so much so that many of our customers were long-established big names in IC design that had sometimes spent years and millions of dollars trying to design a specialty chip that we later did for under a hundred grand and in four months from start of design to testing chips that worked on first silicon.

We once hired a layout technician that had twenty years of experience at Intel and it was a complete disaster. She was completely reliant on the tool chain to do her thinking for her, which worked fine on the type of designs that she worked on at Intel. But we discovered that, for our designs, it really required that the engineer that did the design and simulation needed to be the one to do the layout artwork for the bulk of the chip.

 

Doing design "by hand" could have a multiple interpretations.

One is "cutting ruby" which involved creating a "mask" using blades that was optically reduced to make a reticle (did they call them this before e-beam? I don't recall.).

Another definition could be a draftsman drawing transistors on mylar that were later transferred to a computer by transcribing the drawing.

And yet another definition for "by hand" could be full custom layout where each gate was drawn on a computer by a designer. As opposed to placing and routing standard cells that were hand crafted by someone else. A person or program could determine placement and routing.

 

She was completely reliant on the tool chain to do her thinking for her, which worked fine on the type of designs that she worked on at Intel.

Some of the Intel tools incorporated the design rules and layout designers sometimes trusted the tool more than themselves.

HP Labs developed a system in the 70's that also comprehended design rules.

 

Many CAD tools are design-rule aware. The higher-end tools had all kinds of nice interactive features that show design rule violations in real time as you are working with the layout (as do many PCB layout tools). But satisfying the design rules does not mean the chip is going to work, especially for sensitive analog circuits.

The tools we used were very much on the low end. At a time when the high end tools were about $250,000 per seat with huge annual maintenance licenses, our tools were about $7000, which included schematic capture, simulator, layout editor, design rule checker, netlist extractor, and layout-vs-schematic software. Unfortunately they were from four different venders and were not compatible. We also had to write our own design rule decks and device definition files for the extractor. The upside to them not being integrated was that they could be shared by about four engineers since a given person only needed a couple of the tools at any given time. None-the-less, a fair amount of my time was spent writing code to translate stuff from one tool to another or to do things that the tools couldn't do, such as antenna rule checking once that started becoming a big issue. Another upside, for our niche designs, was that our president knew when, where, and how to violate the design rules to get a chip to do something that the design rules would have made impossible. I used to say that our motto should have been, "We shall fab no chip that doesn't violate at least five design rules." Unfortunately, about the time our designs went to 250 nm, we discovered (very much the hard way) that our days of playing fast and loose with the design rules were over. The rules also became so complicated that it was completely unreasonable for us to even attempt to write our own rule decks any longer and so we had to shell out $20k for a DRC tool that could use the fab house's rule decks. We also had to step up to a higher level simulator.

Still, some of our customers continue to be simultaneously appalled and mesmerized by the designs we make happen with the tools we use.

 

"We shall fab no chip that doesn't violate at least five design rules." Unfortunately, about the time our designs went to 250 nm, we discovered (very much the hard way) that our days of playing fast and loose with the design rules were over.

I was fortunate to work for a group that had close interaction with our fabs for 250nm thru 90nm. We could get detailed reasons for why the rules were the way they were and we were sometimes able to get a rule changed because we were the first production part on the process.

The rules also became so complicated that it was completely unreasonable for us to even attempt to write our own rule decks any longer and so we had to shell out $20k for a DRC tool that could use the fab house's rule decks.

With every new process node, rules got significantly more complex. The last process I wrote design rule checks for was 22nm. For 14nm and 10nm, I wrote supplemental checks. We couldn't contract anyone to do it for us because the information was classified Top Secret.

We used from tools from multiple vendors, including internally developed. Our budget was hundreds of millions per year.

 

We used from tools from multiple vendors, including internally developed. Our budget was hundreds of millions per year.

I remember the hallmark year when our total revenue surpassed one million. I don't know what it is now, but I'm pretty sure it is still below five million. Small company, small budget -- you do what you've got to do.

 

hello,
what was the name of chip you designed can you please share ic pictures your work?

 

I designed (or helped design) a couple dozen chips. We were a design house and we didn't market any of our own chips; we designed chips for other customers who generally integrated them into their products and sold them under their own name. One of our chips is in orbit around Mars as part of the Mars Reconnaissance Orbiter (in particular, the Mars Climate Sounder).

 

1. One of our chips is in orbit around Mars as part of the Mars Reconnaissance Orbiter (in particular, the Mars Climate Sounder

   how it work??
   
   

   we designed chips for other customers who generally integrated them into their products and sold them under their own name.

2. ok great what will be the cost of that chips?

 

1. how it work??

It's a thermal imager. I'm really not at liberty to go into details without getting permission from both my old employer and the customer.

1. ok great what will be the cost of that chips?

Again, not really at liberty to go into those kind of details on a specific chip. In general, the design of a chip ranges from about $50k to $300k and the fabrication can range from $20k to well over a million dollars. Very much depends on the complexity/difficulty of the design, the technology used, and whether the chip can be fabbed on a multi-project wafer or needs a dedicated wafer run. When I first started (1995) we could do some of the simpler designs for about $20k and fab them for about $5k -- boy are those days gone!

 

When I first started (1995) we could do some of the simpler designs for about $20k and fab them for about $5k -- boy are those days gone!

Mask sets for a state of the art process ran about $1M per reticle when I retired.

The later design projects I worked on probably cost around $500 million, so the first few million parts paid for the cost of designing and manufacturing.

 

Most (not all) of our designs were for small-scale, one-off, lunatic-fringe projects. It was not uncommon for the five to fifteen chips that we got from a multi-project run to be sufficient for costumer's entire needs, so dumping those kinds of resources into it in anticipation of a big profit down the road was very seldom a consideration. That meant that we were on very tight budgets for the NRE; on the plus side of that ledger, however, was that the technical specs were usually far, far more important than the physical economics (keeping the die area to the absolute minimum, for instant).

 

When I first started (1995) we could do some of the simpler designs for about $20k and fab them for about $5k -- boy are those days gone!

in 1991 i was born you were working since 1995 great...

the cost of chip was expensive..
what was advantage of that chips?