Hi everyone, I downloaded this circuit, which is a laser driver. But I don't know how it works. Can anyone give a brief explanation? Thanks!

 

The amp at the bottom generates a 5V voltage reference for the amp at the top.

The amp at the top, combined with the resistor, creates a (kinda) current source. That current drives the left transistor, which is mirrored to the right. The mirrored current drives the red thing.

Is that really 2.5V? I don't think this will work well.

 

 

View attachment 75651

How do you figure 4.3V and 358mA?

 

That is not a good Laser Diode driver circuit. This is a simpler, better one, with a good explanation of how it works.

 

Cantata (or are you Aria?),

You avatar is almost as attractive as mine.

 

How do you figure 4.3V and 358mA?

Assumed the op amp is a rail to rail and the power is 5V, the (-) voltage less than (+) voltage of the op amp, and the bjt Vb>Ve=0.7V, Vb=5V, Ve=5V-0.7V=4.3V.
Assumed the fet in the saturation status, I = 4.3V/12 Ω =358mA.
If the power of op amp is changed then all the voltage will be change.

 

Cantata (or are you Aria?),

You avatar is almost as attractive as mine.

Hi, I'm Cantata, Aria is me, too

 

Assumed the op amp is a rail to rail and the power is 5V, the (-) voltage less than (+) voltage of the op amp, and the bjt Vb>Ve=0.7V, Vb=5V, Ve=5V-0.7V=4.3V.
Assumed the fet in the saturation status, I = 4.3V/12 Ω =358mA.
If the power of op amp is changed then all the voltage will be change.

Hi， why Vb=5V, did you assume this value or Vb is equal to (+) voltage of op amp?

 

And I don't know why the op amp on the top is needed .I think the output voltage of the left side op amp can go directly to Base of BJT, and then Ve goes to FET

 

Assumed the op amp is a rail to rail and the power is 5V, the (-) voltage less than (+) voltage of the op amp, and the bjt Vb>Ve=0.7V, Vb=5V, Ve=5V-0.7V=4.3V.
Assumed the fet in the saturation status, I = 4.3V/12 Ω =358mA.
If the power of op amp is changed then all the voltage will be change.

So you are assuming the circuit is designed such that the op amp runs open loop and saturates?

 

And I don't know why the op amp on the top is needed .I think the output voltage of the left side op amp can go directly to Base of BJT, and then Ve goes to FET

If I understand you correctly, I think you are correct, as long as you include the resistor. The constant output voltage of the 1st amp less Vgs across the resistor will establish as stable a current in the left side of the mirror as the original circuit, I think.

My problem with the overall circuit, though, is that the output of the current mirror has little or no compliance. I think 2.5V is an error.

Please see MikeMLs post above. If you only need a current source and no optical feedback for LD output stabilization, use the LM317.

 

Also, you don't need the op amp on the bottom either, if the 12V is stable.

 

Hi， why Vb=5V, did you assume this value or Vb is equal to (+) voltage of op amp?

I assuming that if using a rail to rail op amp then it could be have that 5V output, when the power for op amp is 5V.

 

So you are assuming the circuit is designed such that the op amp runs open loop and saturates?

Assuming that the op amp(rail to rail) is runs as a voltage comparator, and the power 5V for op amp, if using a real voltage comparator the output voltage could be difference, but the result and what I assuming is the same.

 

Why I didn't used 9V or 12V for the op amp or voltage comparator, because I was worried about the output voltage may generate the oscillation, I just did a small testing and the oscillation was really happened.

What I concerned was like this:
When the op amp using 5V for power, then the output will keeping high and the bjt will keeping on, the result is similar as the circuit what i attached on #3.

When the op amp using 9V or 12V for power, if the V- < V+(5V) then the op amp output will be high and around 10.6V, Vb = 10.6V, Ve = 10.6V-0.7V = 9.9V, V-(9.9V) > V+(5V), op amp output will be low and about 0V, when the op amp output became 0V, the Vb=0V, Ve = 0V, Ve(0V) < V+(5V), then the op amp output will be high(10.6V) again, so the oscillating is happening.

 

I have to admit to being totally confused. What prevents the upper amplifier from equalizing its negative input to +5V when the supply is (say) +12V? I didn't build anything but it "works" just fine in simulation using an LM324 or LM358 single supply op amp. Isn't this simply a classical series pass regulator topology?
Admittedly, I just connected the +ve input to a single +5V source rather than the more complicated 5V op amp regulator.

 

I have to admit to being totally confused. What prevents the upper amplifier from equalizing its negative input to +5V when the supply is (say) +12V? I didn't build anything but it "works" just fine in simulation using an LM324 or LM358 single supply op amp. Isn't this simply a classical series pass regulator topology?
Admittedly, I just connected the +ve input to a single +5V source rather than the more complicated 5V op amp regulator.

I also a little confused and I was afraid of what I thought was wrong, so I did the test, but I just connected a 100 Ohms and 3V/20mA led to be the load, and the V+ of op amp I connected to 5V.

You may doing the real connections and using 5V for the power of op amp to do the test, and also using 9V or 12V to be the power for op amp and test again.