Sorry I'm a biginner. I'm learning about how this circuit works and I have questions .

In this circuit C2 is non polarized capacitor :



First it's charged with one side of capacitor ( positive side ) so when it discharge it will follow this path right?


And second it charged with other side( positive side ) so when it discharge it will follow this path right ?


Thank you

 

Why are you concerned about the charge/discharged path of C2?
C2 provides positive feedback to the base of the first NPN transistor. This increases the gain of the driver stage.

 

C2, being a coupling capacitor, is a part that you really don't want to discharge or charge very much because doing so would indicated a problem with the low frequency response. Ideally, the voltage across C2 would remain constant and equal to the average voltage difference between the base of TOT NPN and the collector T1 BC559.

 

@MrChips I disagree - the circuit isn't an amplifier, its an oscillator. The NPN transistor is marked' TOT' = transistor on test; I'm guessing this is some sort of go/no go checker for NPN transistors.

@Heroz Is this homework? You are right that, at power on, Q1 and Q2 are off and C2 starts charging through R3, R1, R5 until the voltage at the base of Q1 turns it on, and that turns Q2 on, pulling OUT to 9v. This rapidly charges C2 through the base of Q1 until Ib1 falls to zero, turning Q1 and Q2 off. OUT falls close to zero, pulled down by R5 and the other end of C2 falls to around -7v. C2 now starts charging again through R3, R5, R1, and the cycle repeats. Q3 (not sshown here) drives the speaker with a tone of around 1.2kHz.

 

@MrChips I disagree - the circuit isn't an amplifier, its an oscillator. The NPN transistor is marked' TOT' = transistor on test; I'm guessing this is some sort of go/no go checker for NPN transistors.

@Heroz Is this homework? You are right that, at power on, Q1 and Q2 are off and C2 starts charging through R3, R1, R5 until the voltage at the base of Q1 turns it on, and that turns Q2 on, pulling OUT to 9v. This rapidly charges C2 through the base of Q1 until Ib1 falls to zero, turning Q1 and Q2 off. OUT falls close to zero, pulled down by R5 and the other end of C2 falls to around -7v. C2 now starts charging again through R3, R5, R1, and the cycle repeats. Q3 (not sshown here) drives the speaker with a tone of around 1.2kHz.

View attachment 279712

Thank you .I found this in project book . I have a question when it discharge it will follow the path I drew right?

 

when it discharge it will follow the path I drew right?

No. The discharge path is R5, C2, TOT base-emitter, R2.

 

Thank you .I found this in project book . I have a question when it discharge it will follow the path I drew right?

Yes, I agree but see discussion below...

No. The discharge path is R5, C2, TOT base-emitter, R2.

Sorry @Alec_t but I think you're wrong. Here's why:

Conventionally 'charge' means to add energy, discharge to remove it as per the 1st circuit below. We add energy in the charge cycle by closing S1/S3, so the capacitor ends the cycle with 10uC of charge (Q = CV), then we discharge it through S2/S4 into R2 ending with 0C of charge.



But consider this 2nd circuit: are we charging/discharging or charging/recharging? At the end of the cycle the capacitor remains charged at 10uC, albeit with the voltage in the opposite direction.



Now come back to the original circuit. On the first cycle after switch on, Q1/Q2 are off and we charge C2 through 9v->R3->R1->C2->R5->0v until Vb1 > 0.6v then Q1/Q2 turn on and we are actively recharging 9v->Q2ec->C2->Q1be->R2->0v until Ib1 drops too low to hold Q1/Q2 on. Then Q1/Q2 turn off, but C2 is still charged. The RH side of C2 drops to near 0v via R5 so the LH side drops to -7v by virtue of the stored charge. This reverse-biasses Q1be junction so no current flows back through Q1/R2 (sorry @Alec_t ). Instead we are recharging C2 again through 9v->R3->R1->C2->R5->0v but with C2 starting with an initial negative charge.

Since no path passively removes energy from C2 I contend we have two charge/recharge paths, but there is no passive discharge path as such. Feel free to disagree!

 

Sorry @Alec_t but I think you're wrong.

Yup. My bad.

 

Yes, I agree but see discussion below...

Sorry @Alec_t but I think you're wrong. Here's why:

Conventionally 'charge' means to add energy, discharge to remove it as per the 1st circuit below. We add energy in the charge cycle by closing S1/S3, so the capacitor ends the cycle with 10uC of charge (Q = CV), then we discharge it through S2/S4 into R2 ending with 0C of charge.

View attachment 279751

But consider this 2nd circuit: are we charging/discharging or charging/recharging? At the end of the cycle the capacitor remains charged at 10uC, albeit with the voltage in the opposite direction.

View attachment 279752

Now come back to the original circuit. On the first cycle after switch on, Q1/Q2 are off and we charge C2 through 9v->R3->R1->C2->R5->0v until Vb1 > 0.6v then Q1/Q2 turn on and we are actively recharging 9v->Q2ec->C2->Q1be->R2->0v until Ib1 drops too low to hold Q1/Q2 on. Then Q1/Q2 turn off, but C2 is still charged. The RH side of C2 drops to near 0v via R5 so the LH side drops to -7v by virtue of the stored charge. This reverse-biasses Q1be junction so no current flows back through Q1/R2 (sorry @Alec_t ). Instead we are recharging C2 again through 9v->R3->R1->C2->R5->0v but with C2 starting with an initial negative charge.

Since no path passively removes energy from C2 I contend we have two charge/recharge paths, but there is no passive discharge path as such. Feel free to disagree!

Thank you. But in your 2nd circuit

Yes, I agree but see discussion below...

Sorry @Alec_t but I think you're wrong. Here's why:

Conventionally 'charge' means to add energy, discharge to remove it as per the 1st circuit below. We add energy in the charge cycle by closing S1/S3, so the capacitor ends the cycle with 10uC of charge (Q = CV), then we discharge it through S2/S4 into R2 ending with 0C of charge.

View attachment 279751

But consider this 2nd circuit: are we charging/discharging or charging/recharging? At the end of the cycle the capacitor remains charged at 10uC, albeit with the voltage in the opposite direction.

View attachment 279752

Now come back to the original circuit. On the first cycle after switch on, Q1/Q2 are off and we charge C2 through 9v->R3->R1->C2->R5->0v until Vb1 > 0.6v then Q1/Q2 turn on and we are actively recharging 9v->Q2ec->C2->Q1be->R2->0v until Ib1 drops too low to hold Q1/Q2 on. Then Q1/Q2 turn off, but C2 is still charged. The RH side of C2 drops to near 0v via R5 so the LH side drops to -7v by virtue of the stored charge. This reverse-biasses Q1be junction so no current flows back through Q1/R2 (sorry @Alec_t ). Instead we are recharging C2 again through 9v->R3->R1->C2->R5->0v but with C2 starting with an initial negative charge.

Since no path passively removes energy from C2 I contend we have two charge/recharge paths, but there is no passive discharge path as such. Feel free to disagree!

@MrChips I disagree - the circuit isn't an amplifier, its an oscillator. The NPN transistor is marked' TOT' = transistor on test; I'm guessing this is some sort of go/no go checker for NPN transistors.

@Heroz Is this homework? You are right that, at power on, Q1 and Q2 are off and C2 starts charging through R3, R1, R5 until the voltage at the base of Q1 turns it on, and that turns Q2 on, pulling OUT to 9v. This rapidly charges C2 through the base of Q1 until Ib1 falls to zero, turning Q1 and Q2 off. OUT falls close to zero, pulled down by R5 and the other end of C2 falls to around -7v. C2 now starts charging again through R3, R5, R1, and the cycle repeats. Q3 (not sshown here) drives the speaker with a tone of around 1.2kHz.

View attachment 279712

I saw your output waveform . In this circuit it's not AC right? Because in my circuit diagram they drew sine wave .

 

Thank you. But in your 2nd circuit

I saw your output waveform . In this circuit it's not AC right? Because in my circuit diagram they drew sine wave .

Well its still 'AC' in the sense its not static DC! Its a pulse waveform.

The 'waveforms' on that original circuit diagram are misleading and unhelpful, IMHO. I think they are really intended to show 'direction' rather than real 'shape'. The true wave forms from the simulation I posted are much more useful in determining circuit function. You cannot beat experience for visual understanding of key circuit blocks and therefore function, but a simulation can clarify the detail. At first glance Q1 in that circuit is configured as a classic small signal common emitter amplifier hence MrChip's understandable error in assessing the functionality led on by those 'sine' waveforms), but here its necessary to see how Q2 behaves to work out overall function and realize that error.

While simulation isn't always an answer, as a beginner I recommend you download LTSpice from Analog Devices and try simulating basic RLC circuits to get an understanding of how you use it.