Figure 1: Block Diagram
I attached my attempt, according to my mem file its supposed to output: 18 18 18 18 35 17
instead it looks like it reads the first address at x0000 rather than x0001
How do I make the circuits act like this block diagram in Verilog?
- Thread starter Precooledear
- Start date
Figure 1: Block Diagram
I attached my attempt, according to my mem file its supposed to output: 18 18 18 18 35 17
instead it looks like it reads the first address at x0000 rather than x0001
