I'm trying to make a countdown timer with the 74LS192 IC. I've already figured out how to set the time but, when the 1st cycle finishes, it loops back to start. Any Suggestions?

 

Welcome to AAC!

Is this schoolwork?

EDIT: This less colorful schematic might be easier for members to read:

We don't put text on top of symbols or wires. You can't do anything about the corny curved wires or the unnecessary logic level indications where pin numbers would be more helpful. Since the simulator supports resistors, you should use one for the LED.

 

You have two choices, count to n and recycle which is what you are doing or count to n and halt which is what I assume you want. Normally you would run your clock through a NAND gate like a 7400 where one input is your clock and the other goes to n. See page 62 of this link for a schematic to work from and give you the idea.

Ron

 

Should not be difficult to figure out how to stop the count when the final count is reached.

 

Welcome to AAC!

Is this schoolwork?

EDIT: This less colorful schematic might be easier for members to read:
View attachment 279377
We don't put text on top of symbols or wires. You can't do anything about the corny curved wires or the unnecessary logic level indications where pin numbers would be more helpful. Since the simulator supports resistors, you should use one for the LED.

Hello! Nope, this isn't schoolwork, just a hobbyist . My simulator is limited in showing that kind of stuff, you have to hover over the pin to show the number. It also makes the turns "Curved" as you said.
Thanks for your feedback on my first post!

 

You have two choices, count to n and recycle which is what you are doing or count to n and halt which is what I assume you want. Normally you would run your clock through a NAND gate like a 7400 where one input is your clock and the other goes to n. See page 62 of this link for a schematic to work from and give you the idea.

Ron

Just exactly what I need! I've been looking at different articles for a while now. Going to post the result once I get it done. Huge thanks!

 

Looks like homework to me, so I moved it

 

Just exactly what I need! I've been looking at different articles for a while now. Going to post the result once I get it done. Huge thanks!

No problem and by all means any further questions just ask.

Ron

 

Nope, this isn't schoolwork, just a hobbyist

1. What is the purpose of decoding the segment outputs of the LS47's instead of the counter outputs?
2. When switches are opened, you're allowing inputs to float.
3. Is this supposed to be a 2 digit counter? Why do you have independent clocks to the counters?
4. You have too many floating inputs.
5. What count do you want the counter to stop at? The decode logic on the upper counter will decode 0 or 8.

 

For most circuits, I find not using NOR and NAND gates easier to read.

If you apply De Morgan's law to the NAND gate, you get the lower equivalent which I find much easier to comprehend.

If you were really doing an AND function, using a NAND would make sense, but you're implementing an OR function, so using OR gates would make more sense.

 

For most circuits, I find not using NOR and NAND gates easier to read.

If you apply De Morgan's law to the NAND gate, you get the lower equivalent which I find much easier to comprehend.
View attachment 279436
If you were really doing an AND function, using a NAND would make sense, but you're implementing an OR function, so using OR gates would make more sense.

Though keep in mind that the lower circuit will have a greater propagation delay and consume more power (assuming that we are talking about a CMOS implementation). If neither of those factors matter, then going with an implementation that is more intuitively obvious to people reading the schematic has a lot of merit. Also, since the 4000 series gates buffer both the input and the output, this generic delay/speed penalty is a lot murkier.

I notice that the schematic is mixing 74LS TTL parts and 4000 CMOS. Care must be taken that the I/O voltage levels and drive strengths are compatible. It's been years since I've looked at that, so I don't know the answer off the top of my head.

 

For most circuits, I find not using NOR and NAND gates easier to read.

If you apply De Morgan's law to the NAND gate, you get the lower equivalent which I find much easier to comprehend.
View attachment 279436
If you were really doing an AND function, using a NAND would make sense, but you're implementing an OR function, so using OR gates would make more sense.

Hello, I've come up with a solution to the problem with the material you sent me (the pdf one). Thank you for the advice! I used a three input AND gate whose output activates/ deactivates a Relay connected to the clock. Now, when the counter reaches 0, it halts. Thank you very much!

 

Glad it worked out for you.

Ron