Hello! Nope, this isn't schoolwork, just a hobbyist . My simulator is limited in showing that kind of stuff, you have to hover over the pin to show the number. It also makes the turns "Curved" as you said.Welcome to AAC!
Is this schoolwork?
EDIT: This less colorful schematic might be easier for members to read:
View attachment 279377
We don't put text on top of symbols or wires. You can't do anything about the corny curved wires or the unnecessary logic level indications where pin numbers would be more helpful. Since the simulator supports resistors, you should use one for the LED.
Just exactly what I need! I've been looking at different articles for a while now. Going to post the result once I get it done. Huge thanks!You have two choices, count to n and recycle which is what you are doing or count to n and halt which is what I assume you want. Normally you would run your clock through a NAND gate like a 7400 where one input is your clock and the other goes to n. See page 62 of this link for a schematic to work from and give you the idea.
Ron
No problem and by all means any further questions just ask.Just exactly what I need! I've been looking at different articles for a while now. Going to post the result once I get it done. Huge thanks!
Nope, this isn't schoolwork, just a hobbyist
Though keep in mind that the lower circuit will have a greater propagation delay and consume more power (assuming that we are talking about a CMOS implementation). If neither of those factors matter, then going with an implementation that is more intuitively obvious to people reading the schematic has a lot of merit. Also, since the 4000 series gates buffer both the input and the output, this generic delay/speed penalty is a lot murkier.For most circuits, I find not using NOR and NAND gates easier to read.
If you apply De Morgan's law to the NAND gate, you get the lower equivalent which I find much easier to comprehend.
View attachment 279436
If you were really doing an AND function, using a NAND would make sense, but you're implementing an OR function, so using OR gates would make more sense.
For most circuits, I find not using NOR and NAND gates easier to read.
If you apply De Morgan's law to the NAND gate, you get the lower equivalent which I find much easier to comprehend.
View attachment 279436
If you were really doing an AND function, using a NAND would make sense, but you're implementing an OR function, so using OR gates would make more sense.
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