In post # 2 circuit, if there is no slow Tr of an input, how does 1 uF get charged rapidly, like within a prop delay of the gate(s) ?

It doesn't get charged rapidly. As in Wally's charts, it sets the switch debounce time constant; different values, same 0.1 s. As with any switch debouncing, it is a tradeoff between long enough to capture all of the bounces, and short enough to allow rapid switch action.

The small cap is optional. It is only 1% of the larger cap, so it charges up almost instantly. I don't know why the original poster of the schematic has it in there (I grabbed it off the innergoogle rather than sketch it). I've used the circuit both with and without, and didn't see any functional difference.

ak

 

I must be missing something. If that cap does not get charged rapidly (which I agree with)
then it presents a slow moving input to the gate, leaving it in its active region for t >> Tpd,
thereby susceptible to what I see in the sims. And what TI talks about in their ap note.

Regards, Dana.

 

I must be missing something. If that cap does not get charged rapidly (which I agree with)
then it presents a slow moving input to the gate,

No, it doesn't. I'll use Wally's schematic because it has reference designators.

Initial conditions: Out =high; U1 input = high; U1 output = low, Vc = 0

Switch press: U1 input = low (instantly)
U1 output = U2 input = high (instantly); Out = low (instantly)

When U1 out goes high, C1 starts to charge (slowly)up through R1. BUT, when the switch is closed, R1 and R2 form a voltage divider between high and low. As long as the switch is held closed, C1 charges up only to this node voltage, not the high-state voltage. As long as R2 is significantly smaller than R1, the node voltage does not approach the CMOS input transition level. That is a potential problem with the schematic in post #2 (now flagged). When the switch opens, C1 resumes slowly charging up to Vhigh, but none of the gate inputs see this slow ramp.

Is that what you missed?

ak

 

If that cap does not get charged rapidly (which I agree with)
then it presents a slow moving input to the gate,

That slow charge/discharge occurs after the switch opens and is not seen by the gate.
Take a look at the cap voltage (red trace) in relation to the switch state in my simulation results, post #9.

 

I made the mistake and the circuit should look like this:


Now I see the chance that this circuit can indeed work. If we ignore the unpredictable initial condition at start-up.
The SW1 will force the Vout 1 to low state. And SW2 will reset Vout1 and set Vout2 at low state.
What do you guys think?

 

What do you guys think?

It won't work reliably since both of the reset inputs are pulled low through the diodes, so the state of the latch with the pressed button is indeterminate when the button is released.

If you just want alternate action, that can be done with one latch and no diodes (below).

 

The SW1 will force the Vout 1 to low state.

No, it won't. It will force pin 3 to a high state, but that high will not propagate to the output.

SW1 also will pull IC1B low through diode D1. This will force pin 4 high, ignoring whatever is going on at pin 5. It will unambiguously reset any downstream stages, but the stage being activated still will be indeterminate when the button is released.

ak

 

If you just want alternate action, that can be done with one latch and no diodes (below).

But what if I want to control more device than two? So, using this circuit we can "stack more" of these circuits to get more output controlled via microswitch witch only one can be ON at once. I don't know If I make myself clear here. The SW1 will reset all the flip-flops (high state) and when SW1 is released it will force Vout 1 at Low and the and the remaining flip-flops will be at High state (reset) at his outputs.

No, it won't. It will force pin 3 to a high state, but that high will not propagate to the output.

But this diode will make the difference. After SW1 button was released thanks to the diode the High state will "appear" a little bit faster at pin 6 than at pin 1. And this will set IC1B output to the low state.

 

The small cap is optional. It is only 1% of the larger cap, so it charges up almost instantly. I don't know why the original poster of the schematic has it in there

The .01uf cap insures that the output is low on power up if that is a concern.
SG

 

The .01uf cap insures that the output is low on power up

Good point. Thanks.

ak

 

Breadboarded the circuit in post #25 (Jony130) and confirmed it does not work as suggested.
On power up both outputs are either low or high, random
If outputs are low after power up: Press S1 or S2 and both outputs go high.
If outputs are high after power up: Press S1 or S2 and both outputs remain high no change.
SG

 

But this diode will make the difference. After SW1 button was released thanks to the diode the High state will "appear" a little bit faster at pin 6 than at pin 1. And this will set IC1B output to the low state.

That's very poor design practice and should not be done.
Just use the circuit I posted in post #27.

 

I found this circuit

Where?

Link?

ak

 

Where?

Link?

ak

https://ep.com.pl/files/7773.pdf

 

Just use the circuit I posted in post #27.

But what If I want more outputs?

 

Breadboarded the circuit in post #25 (Jony130) and confirmed it does not work as suggested.
On power up both outputs are either low or high, random
If outputs are low after power up: Press S1 or S2 and both outputs go high.
If outputs are high after power up: Press S1 or S2 and both outputs remain high no change.

What gate type did you use? VDD = ? And tomorrow after work, I will try to build the circuit too.

 

What gate type did you use? VDD = ?

4011B 5vdc
SG

 

But what If I want more outputs?

Outputs to do what?
How many?
One output can go to more than one input.

 

Just a thought but if you need to handle a number of buttons a small
processor like a ATTINY makes sense. Code would be pretty simple,
power up state would be guaranteed, buttons fully debounced, no external
components other than 1 cap for processor supply bypass.

Could do the code with one of the graphical languages like Ardublock, Blocky
Arduino, Blocky for Picaxe....or just use Arduino IDE and language. Already
examples available.

http://www.makersbox.us/2014/01/Scratch.html

How many buttons do you need to handle ?


Just a thought.

 

Outputs to do what? How many?

Without conceding that the circuit works reliably, one nice feature is that it is pretty much infinitely expandable (unlike circuits that use some form of physical OR gate to combine switches for reset signals). It is electrically very similar to a switch bail, a mechanical bar that releases any buttons not pressed (think old mechanical car radio station buttons).

Thinking out loud, adding a diode and small capacitor to each stage would guarantee that the activated stage would stay set after the common reset signal had returned high. Or something like that.

I've never been good at finding relevant old threads, but I think we went down this road a few months ago.

ak