Hi, in my project I have to design a subtractor. In this design i can only use these ones : AND Gate, XOR Gate, an Adder and a Circular Left Shifter. Like in the image below.
How can i design this with these givens (I don't have to use all of them) ?

 

Mr. WBahn answered this like "What is A XORed with a 1?" and that's true. This works like a NOT gate. Thank you.

 

Hi, as I mentioned above i need to design a subtractor. I designed ALU and a register block. But, I didn't create the Control Unit. My top module is like in the image below. I also add my RB and ALU codes if they're true can someone help me to write a CU code for verilog ?

The calculation processor must do is :




(When start is "1" CU starts calculating and during this busy out is "1").

------------------------------------------- ALU code(This may be wrong)
module ALU(
input [1:0] InsSel,
input [7:0] ALUinA,
input [7:0] ALUinB,
reg [7:0] ALUOut,
output CO,
output Z
);

always@(*) begin
case(InsSel)
2'b00 : begin ALUOut <= ALUinA & ALUinB; end
2'b01 : begin ALUOut <= ALUinA ^ ALUinB; end
2'b10 : begin ALUOut <= ALUinA + ALUinB; end
2'b11 : begin ALUOut <= ALUinA << ALUinB; end

default ALUOut = 8'b0;
endcase
end

endmodule

------------------------------------------------- RB code(this must be true)

`timescale 1ns / 1ps
module RB(
input clk,
input [2:0] InMuxAdd,
input [3:0] OutMuxAdd,
input [7:0] InA,
input [7:0] InB,
input [7:0] ALUout,
output [7:0] ALUinA,
output [7:0] ALUinB,
input [7:0] CUconst,
input [3:0] RegAdd,
output [7:0] Out );

reg [7:0] RegOut;

reg [7:0] Registers [3:0];
reg [7:0] RegIn = 8'h00;

always@(*)begin
case(InMuxAdd)
3'b000: RegIn <= InA;
3'b001: RegIn <= InB;
3'b010: RegIn <= ALUout;
3'b011: RegIn <= RegOut;
3'b100: RegIn <= CUconst;
default: RegIn <= 8'h00;
endcase
end

always@(posedge clk)begin
Registers[RegAdd] <= RegIn;
end

always@(OutMuxAdd)begin
RegOut <= Registers[OutMuxAdd];//OutMuxAdd];
end

assign Out = Registers[0];
assign ALUinA = Registers[1];
assign ALUinB = Registers[2];

endmodule