Hi,

I am looking for a method to design a clock divider in verilog which devides by 31 from 1GHz reference clock

Please advice,
thx

 

A counter and comparator is how I implement clock dividers where the division is not a power of two. You set the comparator to half the division you want. You have the comparator toggle the output of a flip-flop and reset the counter when it reaches the desired count. However, in your case that number would be 15.5, which is not an integer.

However, you will get the same output if you multiply your reference clock by two and then divide by 62 (setting the comparator to look for 31).

I don't think you can make a clock multiplier in Verilog, however, Xilinx and Altera both have modules included on their FPGAs which will perform clock multiplication (DCM and PLL, respectively). The counter and comparison code is straight-forward, so I'll leave that to you.

 

I have seen people use an exclusive-or gate and an inverter to multiply a clock by 2.
Take a clock signal and apply it to one input of the XOR gate, invert the signal and apply it to the other input.

The only thing you need to be aware of is the prop delay of the inverter.