Does the high clock speed make cpu warm

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Werapon Pat

Joined Jan 14, 2018
35
does the high clock speed make cpu warm? if somehow I'm able to replace the clock signal with something that won't make heat,
but the bits or data still synchronize. will that decrease the temperature in the cpu?
( for more detail, I'm just finding the topics for my senior project and I try to think based on problems and the heat problems is what I've found. )
 

WBahn

Joined Mar 31, 2012
25,224
In CMOS-based processors, the amount of heat dissipated is primarily due to charging and discharging the various capacitances associated with the gates. The more times that happens each second, the more power gets dissipated.
 

dl324

Joined Mar 30, 2015
9,985
Power dissipation in microprocessors is primarily affected by clock frequency, supply voltage, and process technology. If you can't change any of the major contributors, you improve heat sinking. Overclockers use water or more exotic heat sinking strategies.

Microprocessors deal with it by varying supply voltage, operating frequency, and/or putting cores/functional blocks to sleep (one of many sleep states).
 
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eetech00

Joined Jun 8, 2013
1,835
does the high clock speed make cpu warm? if somehow I'm able to replace the clock signal with something that won't make heat,
but the bits or data still synchronize. will that decrease the temperature in the cpu?
( for more detail, I'm just finding the topics for my senior project and I try to think based on problems and the heat problems is what I've found. )
Hi

Yes...it will run hotter.
Generally speaking, the faster the clock, the less CPU "Off" time, so the less time the CPU has to cool.
FYI: I have my computer overclocked to 4.5 Ghz….It has a water cooler.

I don't understand this statement:
"if somehow I'm able to replace the clock signal with something that won't make heat,"

eT
 

ian field

Joined Oct 27, 2012
6,539
In CMOS-based processors, the amount of heat dissipated is primarily due to charging and discharging the various capacitances associated with the gates. The more times that happens each second, the more power gets dissipated.
You've pretty much got it - but slowing the clock can also increase dissipation if in some cases it slows switching transition times.
 

andrewmm

Joined Feb 25, 2011
158
You've pretty much got it - but slowing the clock can also increase dissipation if in some cases it slows switching transition times.
This is the digital forum

In alog, yes using a slow edge speed to a fet causes more dissipation as switch is partly on for longer,
but in digital, even feeding a sine wave clock into the chip, will result in a full edge speed internally,
 

dl324

Joined Mar 30, 2015
9,985
but in digital, even feeding a sine wave clock into the chip, will result in a full edge speed internally
Digital is a subset of analog. Edge transition times affect power dissipation in CMOS designs (which make up the bulk of CPU designs). The range of tolerable transition times is typically limited and specified.
 

ian field

Joined Oct 27, 2012
6,539
This is the digital forum

In alog, yes using a slow edge speed to a fet causes more dissipation as switch is partly on for longer,
but in digital, even feeding a sine wave clock into the chip, will result in a full edge speed internally,
AFAIK: it happens in BBD chips and old unipolar MOS memories. Largely eliminated in modern devices - but it never hurts to put some research behind your put downs.
 

ebp

Joined Feb 8, 2018
2,332
There is nothing you can do externally with the clock to reduce power consumption other than reducing the frequency. It isn't the clock itself that is responsible for generating heat but all of the events that happen as a result of that clock. Power consumption in VLSI is a major concern and huge amounts of effort have gone into the topic.

"... but in digital, even feeding a sine wave clock into the chip, will result in a full edge speed internally,"
This is false unless something internal to the IC, typically a Schmitt trigger, cleans up the transition times. A great many digital ICs will malfunction with slow clock transitions. Datasheets will specify the allowable rise and fall times. For example, for the PIC12F675, the maximum rise and fall times for an external clock are 15, 25 or 50 ns, depending on configuration.
 
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