I am trying to simulate a zero crossing detection circuit from analog systems LTSpice. I am sensing the resonant current in my resonant half bridge design with a sense resistor, and attempting to generate a PWM switching waveform when the current crosses the zero mark.

It looks as though the circuit is indeed detecting the zero crossing point, but the result is not what I expect - please see attached which shows the translated sensor voltage (blue) and the resultant output from the fast comparator (green).

My switching frequency is 300kHz, but may be increased eventually. I am unsure whether the issue is that the analog circuit is unable to detect the zero crossing points at this frequency.

If there are any suggestions for this circuit or even alternative, better performing circuits then please do let me know.

 

Hi S,
Please post your LTS asc file.
E

 

Hi S,
Please post your LTS asc file.
E

Hi Eric, it should be attached now, also with .asy files, .lib files etc included.

Thanks, S

 

I don't use LTSpice so I can't read your .asc file, and the diagram you posted in post #1 doesn't show where the LT1116's outputs are connected. But looking at the waveforms you show, to me they are exactly what I would expect if the LT1116 was attempting to drive a significant capacitance connected from output to ground; although the comparator is detecting your zero crossings quickly, the output slew rate is very low. To get good, sharp output transitions you need to keep load capacitance as small as possible.

 

I don't use LTSpice so I can't read your .asc file, and the diagram you posted in post #1 doesn't show where the LT1116's outputs are connected. But looking at the waveforms you show, to me they are exactly what I would expect if the LT1116 was attempting to drive a significant capacitance connected from output to ground; although the comparator is detecting your zero crossings quickly, the output slew rate is very low. To get good, sharp output transitions you need to keep load capacitance as small as possible.

Thanks for your reply. I understand your point. At the moment, I have not got the outputs of the comparator driving anything. It is my view that eventually they will be an input to an isolated gate driver, which will then drive my bridge FETs according to the zero crossing detection points of the resonant current. Note I am using GaN transistors which are quite low capacitance. Is the load capacitance being low the only thing to consider when aiming for high output slew rate from the comparator?

 

Is the load capacitance being low the only thing to consider when aiming for high output slew rate from the comparator?

No. Input signal amplitude is another factor that will influence response time and slew rate. The lower the input signal amplitude, the longer and slower the comparator's response will be.

 

No. Input signal amplitude is another factor that will influence response time and slew rate. The lower the input signal amplitude, the longer and slower the comparator's response will be.

I replaced my sense resistor with an AC source of 10V. I don't see any difference in the slew rate of the comparator. I am also confused because I am not driving a capacitive load at the moment, so that shouldn't limit the slew rate either!

Edit: Are you sure that an increased amplitude will further limit the slew rate? From what I have seen, reducing the amplitude will reduce the slope, and therefore the response should be better, not worse.

 

I replaced my sense resistor with an AC source of 10V.

Keep in mind the limitations listed in the datasheet's Absolute Maximum Ratings: the voltage on the comparator inputs absolutely MUST NOT be allowed to go below -0.3 volts, nor above +15 volts, to avoid catastrophic damage.

I don't see any difference in the slew rate of the comparator.

Well, something is sure causing it; you're seeing slew rates several hundred times slower than what you should be seeing.

Try making a simple test circuit in LTSpice with the LT1116's (-) input grounded and the (+) input connected to a PULSE source with 1 ns rise & fall times and an amplitude of +/- 50 mV. You should see a clean output wave with nomore than 20 ns or so propagation delay and very fast rise/fall times.

 

Well, something is sure causing it; you're seeing slew rates several hundred times slower than what you should be seeing.

Try making a simple test circuit in LTSpice with the LT1116's (-) input grounded and the (+) input connected to a PULSE source with 1 ns rise & fall times and an amplitude of +/- 50 mV. You should see a clean output wave with nomore than 20 ns or so propagation delay and very fast rise/fall times.

Okay, bear with me here. I have tried what you have outlined, and the results did not really change when I put the circuit into my current design. However, when I started a new .asc file and ran it there, the output looks more like what you would expect, but with some kind of erratic behaviour when triggering the output ON. I will include a simulation.

I am unsure why I get different results when I simulate the circuit alone, and then when I place it within my circuit. Strange. I also don't understand the erratic behaviour. Maybe you can provide insight there?

 

I am unsure why I get different results when I simulate the circuit alone, and then when I place it within my circuit. Strange. I also don't understand the erratic behaviour. Maybe you can provide insight there?

Ya got me; I'm all out of ideas. Maybe someone else, more familiar with LTSpice than I, can help.

 

I looked at the data sheets and took a stab a simulating it like this:

With waveforms marked:



I was just working off the TP original image. Perhaps this will help. I know, I some how set it to 308kHz.... just imagine it's 300kHz.

 

I looked at the data sheets and took a stab a simulating it like this:

View attachment 193335 With waveforms marked:

View attachment 193336

I was just working off the TP original image. Perhaps this will help. I know, I some how set it to 308kHz.... just imagine it's 300kHz.

What simulation software is this, may I ask?

Ok, it seems to be working now (not in my simulation, but in a seperate file). For some reason unknown to me, as soon as I place the circuit into my main simulation it does not work as expected!! Furthermore... Is there a reason why the output pulse, however, is offset from 0V? Is there a way I could shift it to be 0-6V or some other value like-3 to 6V for a gate drive?

Btw, nice name, wish I had thought of that!

 

What simulation software is this, may I ask?

Ok, it seems to be working now (not in my simulation, but in a seperate file). For some reason unknown to me, as soon as I place the circuit into my main simulation it does not work as expected!! Furthermore... Is there a reason why the output pulse, however, is offset from 0V? Is there a way I could shift it to be 0-6V or some other value like-3 to 6V for a gate drive?

Btw, nice name, wish I had thought of that!

simulator: everycircuit.com

It isn't good for anything super sophisticated, but it can help you do some quick and dirty stuff.

 

For some reason unknown to me, as soon as I place the circuit into my main simulation it does not work as expected

What else is OUT connected to in the main simulation?
Remove the OUT node name from the comparator output and see if that makes a difference.

 

What else is OUT connected to in the main simulation?
Remove the OUT node name from the comparator output and see if that makes a difference.

Thanks for your reply! Absolutely nothing. It is a node I called only for that output. Removing the node name has the same result. I am absolutely baffled! The only thing I can imagine, is that it is something to do with the MOSFET capacitance, or the cap connected across the drain-source of the MOSFET... but else, I have no idea. I have simulated the design with PLECS now using ideal components, and the function is exactly as I expect... :/