High Frequency Digital Design - Y junction

Thread Starter


Joined Sep 14, 2020
Good Day,

I am designing a digital circuit for DDR3 running at 800 Mhz. On the PCB, I would like to split off the Address and Data lines in order to monitor their signal via an FPGA.

Address lines are Driven by the controller and have resistive terminations, however, Data lines are bidirectional and use On-chip Terminations at the DDR3 memory side. I drew "Circuit_1" to illustrate the circuit.

Now, my concern are:

1. Since I can't ensure that both the traces going to the DDR3 memory and those going to the FPGA will be the exact same length, there will be reflections coming back to the Y-junction.

2. Data lines are bidirectional and therefore, even if I do manage to match the traces exactly, I will encounter the same issue in reverse when the signal is driven by the DDR3 memory.

As a possible solution, I have designed the circuit shown in "Circuit_2". Essentially, I'm simply probing the lines using high a high impedance (1000 ohm) resistance

1. The 1000 ohm resistor will limit the impact of the monitoring traces on the Controller-Memory interconnection.

2. Since I am placing a 50 ohm resistor to GND immediately following the 1000 ohm Resistor, I am limiting the inductive impact of this monitoring line.

3. With the voltage divider set by the 1000 ohm and 50 ohm resistor, the resulting signal will be reduced by a factor of 0.05, however, I should be able to read and amplify this signal with the FPGA.

Could someone with experience in the design of high frequency circuit either confirm if my design is suitable, if I am missing a key element, or if there is a more convenient solution to the problem at hand.

Thank you!



Deleted member 115935

Joined Dec 31, 1969
You will have enough problems running DDR3,
the timing constraints are quiet tight on DDR3.

if you do want to do this,
you are going to have to run 3D signal simulation of the PCB,
which is not cheap and is not fast to do,