Hello! I am currently creating a logic gate schematic for a binary calculator that i am planing on building. Right now i am working on a small SR-latch memory for the calculator but i have run into some problems. The idea is that the input is going to alternate it's saving location between the memory's/SR-latches, but when i press the button which sends the input to the memory both Memory 1 and Memory 2 gets set which is not what i want! If some wise sole knows how to fix my problems i would be very great full.
The counter in the circuit is set to give a signal every other input that it gets.

In the following picture i have made a "block diagram" over how the circuit is suppose to work. I will also try to attach the logism file to the following post.

 

Download link to the logism file because the file format isn't supported as an attachment.
https://filenurse.com/download/cfb0759f1935086e75e84d7a0f025c85.html
If you have logism just right click the file and open with logism.

 

hi AX,
Welcome to AAC.
I assume that the Counter is a D type latch, rising edge triggered from the PB.?
Have you allowed for the propagation delay of the Q output relative to the high going clock edge.
E
Further Note:
Also the memory latches are Level triggered.
Do you follow that OK.?

 

Appreciate the swift response. Apologies for the spelling mistakes in the main post.

The SR-latch is actually a D-type latch like you said (i'm pretty new to these things).
The counter is pretty much a decade counter made to reset and send out signal on it's second output pin.
I do not think that the propagation delay will impacts the circuit in any noticeable way.

I have also only tried the circuit on Logisim and not with actual IC's, maybe it's just the program?

 

Start small. You are building up a big portion of your circuit (though thankfully not the entire thing, which is what many people would charge ahead and do) and then wondering why it doesn't work, leaving yourself a big debugging challenge.

Forget about all the memory latches until you get JUST the toggle circuit working. So do detailed simulations on JUST the far right hand side of the circuit (the button, decade counter, inverter, and two AND gates).

Look VERY closely at the output of both AND gates just after the button is pressed. I think you will find that because you are sending the output of the button to both AND gates at the same time you are sending it to the counter, the AND gate that is enabled before the button press gets turned on by the button press until the counter output changes, at which point the other one gets enabled for the remainder of the button press. End result, both banks get written to on each button press.

This is the big downside to choosing to use asynchronous logic -- the burden becomes yours to identify and deal with all of the possible glitch and race conditions than can possible occur.

 

Is this a homework or just your personal practice?

 

hi Ax,
Consider this, say Q is Low and of course /Q is High.
You push the button, the Clock into the D latch goes High, but at the same instant Q is still High, so one memory block is clocked to store Data.
A few tens of nanosecs later the /Q goes High, But the Clock is still High while you are still pushing the button, so the other memory block is clocked to save Data.!
This is because the Memory blocks are Level activated latches.
Delay the Clock that is going to the two AND Gates [ not the D type clock]

In that way a Memory Clock will not be sent out until the D type latch has been Set.
OK.

E

 

eric beat me by 3 minutes.

Also, switch bounce will cause the counter to toggle many times in a few milliseconds.

ak

 

Is this a homework or just your personal practice?

Personal practice for a school project

 

Start small. You are building up a big portion of your circuit (though thankfully not the entire thing, which is what many people would charge ahead and do) and then wondering why it doesn't work, leaving yourself a big debugging challenge.

Forget about all the memory latches until you get JUST the toggle circuit working. So do detailed simulations on JUST the far right hand side of the circuit (the button, decade counter, inverter, and two AND gates).

Look VERY closely at the output of both AND gates just after the button is pressed. I think you will find that because you are sending the output of the button to both AND gates at the same time you are sending it to the counter, the AND gate that is enabled before the button press gets turned on by the button press until the counter output changes, at which point the other one gets enabled for the remainder of the button press. End result, both banks get written to on each button press.

This is the big downside to choosing to use asynchronous logic -- the burden becomes yours to identify and deal with all of the possible glitch and race conditions than can possible occur.

Yeah i have realized just this. My first schematic was very large and ended up not working at all..

 

Personal practice for a school project

aka, homework.

BTW: You seem to be doing it far better then most. You ARE "practicing" before just cobbling something together the night before it's due, and you are trying to build and test things in pieces and understand why they aren't working. So keep at it and we will be more than happy to keep supporting your efforts.

 

hi Ax,
Consider this, say Q is Low and of course /Q is High.
You push the button, the Clock into the D latch goes High, but at the same instant Q is still High, so one memory block is clocked to store Data.
A few tens of nanosecs later the /Q goes High, But the Clock is still High while you are still pushing the button, so the other memory block is clocked to save Data.!
This is because the Memory blocks are Level activated latches.
Delay the Clock that is going to the two AND Gates [ not the D type clock]

In that way a Memory Clock will not be sent out until the D type latch has been Set.
OK.

E

Thanks, will downscale the schematic and look into this.

 

Yeah i have realized just this. My first schematic was very large and ended up not working at all..

Yep. This is one of those lessons that most of us just simply have to learn on our own, usually by biting of more than we should have and wasting hours trying to figure out what's wrong only to have it shown to us (or figuring out on our own the hard way, which is the far better teacher) that a smaller bite would have made the problem obvious in a couple minutes. Most of also have to have that lesson repeated a few times before we grasp the fact that the first time was the rule rather than the exception.

Engineering is both an art and a science -- the art is learning from your own mistakes, while the science is learning from the mistakes of others.

 

MOD NOTE: Moved to Homework Help.