Cheers everyone. I designed the attached circuit but it is not quite doing what I wat it to do. It works like this:

The clock drives this logic circuit that passes through a tri state buffer. This tri state buffer (74241) is continuously help open by a D flip flop (7474) to ensure the path for the clock is always open. There is a point in my logic circuit where 4 outputs are high, which drives a 4 input AND gate. This passes through an inverter, to generate low signal, where I send the signal 2 separate ways.

1) To the CLR pin of the 7474 (low signal triggers clr on 7474) which sets the output Q low which turns off the tri state buffer.

2) Through a delayed pulse circuit (which is also triggered on the falling clock edge) which produces a high pulse after 1.1RC. Once this pulse is generated it passes through another inverter to the Flip Flop which turns the output back high and tri state buffer back on.


The idea is the tri state buffer is turned off, then after the delayed pulse it turns back on.


The problem is the following. Once the low signal comes out of the first inverter after the AND gate, it turns the tri state buffer off as it should so no more clock signnal can get through. However, the delay pulse is not getting triggered at the same time because the tri state buffer remains off. It is like the tristate buffer is turned off before the delayed pulse (2 555 timers) can be triggered. I even put an LED at the output of teh AND gate,and it remains on once the tristate buffer is turned off.

 

Setting up 555 timers in monostable mode can be a bit tricky. Can you post a schematic of the 555 timers so that we can evaluate the design for possible bugs?

hgmjr

 

Sure I attached it. From what I can recall I tested the timer circuit and it works fine. Somehowit is not getting triggered when the signal splits to delay circuit and flip flop.

Timer 1 output pulse acts as a delay, then triggers timer 2 for the actual output pulse.

 

The first problem that I see with your circuit is that you have the "CONTROL VOLTAGE" input on pin 5 tied to 5 volts. This pin is ordinarily left open and bypassed with a 0.1 uF cap to ground.

hgmjr

 

Also, pin-8 is open when it should be tied to 5 volt power.

Is it possible that you have a pinout error in your diagram?

If not, you need to take a close look at your connections.

hgmjr

 

Sorry, my schematic was wrong. I do have pin 5 tied to ground with a cap and pin 8 tied to Vdd. I just checked my timer circuit and it is workign fine. To test, I put a large cap on the first 555 to generate a long delayed pulse so I can see it go high on the scope. Then when it drops back down to 0 the LED at the output of my 2nd 555 lights up for 1.1RC.

I was thinking about what could be wrong but I need some suggestions. So the 555 is triggered on a low pulse. When the output of my AND gate becomes high, it goes through the inverter and shuts off the tri state buffer. Since the path from clock to the circuit is cut off nothing else happens, so the AND gate remains high. My questions is, does the 555 need to have a complete high --> Low --> back to high to trigger? All it is getting now is high --> low. If I change this, then the output of inverter will go back high and turn the buffer on again, which would just bypass the whole timer aspect. Any thoughts?