Cheers everyone. I have a problem with a circuit and I need some help. I posted this a while back but I have not had much time to work on it since then. I designed the attached circuit but it is not quite doing what I wat it to do. It works like this:
The clock drives this logic circuit that passes through a tri state buffer. This tri state buffer (74241) is continuously help open by a D flip flop (7474) to ensure the path for the clock is always open. There is a point in my state machine logic circuit where 4 outputs are high, which drives a 4 input AND gate. This passes through an inverter, to generate low signal, where I send the signal 2 separate ways.
1) To the CLR pin of the 7474 (low signal triggers clr on 7474) which sets the output Q low which turns off the tri state buffer.
2) Through a delayed pulse circuit using 2 555 timers which is also triggered on the falling clock edge (first 555 serves as delay and second generates the output pulse) which produces a high pulse after 1.1RC. Once this pulse is generated it passes through another inverter to the Flip Flop which turns the output back high and tri state buffer back on.
The idea is the tri state buffer is turned off, then after the delayed pulse it turns back on.
The problem is the following. Once the low signal comes out of the first inverter after the AND gate, it turns the tri state buffer off as it should so no more clock signnal can get through. However, the delay pulse is not getting triggered at the same time because the tri state buffer remains off. It is like the tristate buffer is turned off before the delayed pulse (2 555 timers) can be triggered. I even put an LED at the output of the AND gate,and it remains on once the tristate buffer is turned off.
The delay circuit works fine if I don't connect the output of the inverter after the AND gate to the CLR pin of the D Flip Flop.
I know this may seem confusing, but does anyone have any ideas why my delay circuit won't work when the circuit is completed? Any suggestions would be great! Thank you very much!!!!
The clock drives this logic circuit that passes through a tri state buffer. This tri state buffer (74241) is continuously help open by a D flip flop (7474) to ensure the path for the clock is always open. There is a point in my state machine logic circuit where 4 outputs are high, which drives a 4 input AND gate. This passes through an inverter, to generate low signal, where I send the signal 2 separate ways.
1) To the CLR pin of the 7474 (low signal triggers clr on 7474) which sets the output Q low which turns off the tri state buffer.
2) Through a delayed pulse circuit using 2 555 timers which is also triggered on the falling clock edge (first 555 serves as delay and second generates the output pulse) which produces a high pulse after 1.1RC. Once this pulse is generated it passes through another inverter to the Flip Flop which turns the output back high and tri state buffer back on.
The idea is the tri state buffer is turned off, then after the delayed pulse it turns back on.
The problem is the following. Once the low signal comes out of the first inverter after the AND gate, it turns the tri state buffer off as it should so no more clock signnal can get through. However, the delay pulse is not getting triggered at the same time because the tri state buffer remains off. It is like the tristate buffer is turned off before the delayed pulse (2 555 timers) can be triggered. I even put an LED at the output of the AND gate,and it remains on once the tristate buffer is turned off.
The delay circuit works fine if I don't connect the output of the inverter after the AND gate to the CLR pin of the D Flip Flop.
I know this may seem confusing, but does anyone have any ideas why my delay circuit won't work when the circuit is completed? Any suggestions would be great! Thank you very much!!!!
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