I am designing a current DAC (NMOS element) that sinks the output of another current DAC (PMOS element). For biasing the NMOS, I connected the gate of each transistor to its drain through a switch driven by a select bit, and the drain is connected to the output of the DAC. I am concerned if this would work well as the select bits are synced with a clock so there is constant switching between the gate and drain, hence involving the possibility of charge injection. Can you help me with ideas for biasing the NMOS?

 

Just for further information, the smallest current output from the PMOS current DAC is 6uA, and the step size of the sinking current DAC (64 unit elements) has to be 6uA/256.

 

Please upload the schematic as 800x600 .jpg or .gif file.

 

6uA/256.

You are working in the neighborhood of 23 nanoamps per leg and that is so small that leakage currents and temperature become a consideration for an array of 64 elements. That's why nobody can make predictions unless we see what shape your circuit is. If your design is going to fall on it's face, we'll tell you, but there's no guessing going to happen without more information.

 

Also, for a circuit this delicate, PCB layout is extremely important. But we all seem to agree that a schematic is imperative if you really want other people's advice in this place.