I am trying to design a simple buck converter that will accept input of upto 150V and output 15V using the above circuit i got from the internet. After carefully checking the circuit, i became a bit confused and i would need some explanations from fellow engineers in this forum.

First is about the mosfet. The mosfet used is a N-Channel mosfet, and to fully turn on an n-channel mosfet, its source pin has to be reference to GND and if its not, then its gate pin has to be bootstrapped. Looking at the circuit diagram above, the source pin of the mosfet has no reference to ground, and the gate is not bootstrapped as well, so how will it work?

Second is the totem-pole at the output of the IC, it seems to be connected in reverse direction, is this intentional or a mistake?

Third is the UC3845 IC itself, the IC and all its external components have no reference to GND, instead the GND of the IC is tied to the source pin of the mosfet (which does not have GND reference either), so how is this suppose to work?

From this same circuit, i have seen two different Youtube videos that claimed to use this same circuit and it worked, but i'm a bit confused how manage it could work. Here are the links to the video for reference:

Please i need some explanations.

 

I think there are multiple mistakes on your schematic.

 

I think there are multiple mistakes on your schematic.

Could you please point them out? Thanks

 

Pin 5 GROUND on the 3845 is connected to the switch point (Between Q1 & L1) and the FB pin 2.

 

Pin 5 GROUND on the 3845 is connected to the switch point (Between Q1 & L1) and the FB pin 2.

The entire UC3845 is bootstrapped, so that part of the circuit is correct. The UC3845 power supply capacitor is charged up during the OFF phase of the MOSFET when the MOSFET source goes 0.6V below ground. The capacitor charges up to the same voltage as the output, and therefore the supply voltage represents the output voltage, so can be used to derive Vfb.
A lot of Power Integrations' LinkSwitch-based buck regulators work this way.

. . . but the complementery emitter follower is reversed.

 

The entire UC3845 is bootstrapped, so that part of the circuit is correct. The UC3845 power supply capacitor is charged up during the OFF phase of the MOSFET when the MOSFET source goes 0.6V below ground. The capacitor charges up to the same voltage as the output, and therefore the supply voltage represents the output voltage, so can be used to derive Vfb.
A lot of Power Integrations' LinkSwitch-based buck regulators work this way.

. . . but the complementery emitter follower is reversed.

Thanks for the explanation, but I'm still a bit confused. When the mosfet gate is low, the source pin is 0.6v below gnd and the capacitor charges to the same as input voltage, now, when the gate of the mosfet goes high, the mosfer source pin voltage becomes the same voltage at the drain pin, and as we know, the Gate voltage of a n-channel mosfet must be 8v higher than it's source voltage. In this case ,I'm expecting the mosfet not to turn on. So pls explain to me, how will it keep turned on despite the fact that the source voltage is more than the gate voltage (assuming input voltage is 60v)

 

C10 is connected between the Vcc pin of the IC and the MOSFET source, and it charges up to the output voltage (15V), so it remains at 15V above the source all the time, powering the IC.
The IC output can go to its Vcc pin to turn the MOSFET on, so it can always get the gate to 15V above the source.

 

C10 is connected between the Vcc pin of the IC and the MOSFET source, and it charges up to the output voltage (15V), so it remains at 15V above the source all the time, powering the IC.
The IC output can go to its Vcc pin to turn the MOSFET on, so it can always get the gate to 15V above the source.

Oh yes, that's very correct. I understand now, thanks for pointing that out. But one question still remain, the totem pole connection seem off, the positive voltage is suppose to be at the collector of the npn transistor while the ground should be at the collector of the pnp, but it's in the other way round. Is this a mistake or it is intentional ?

 

Oh yes, that's very correct. I understand now, thanks for pointing that out. But one question still remain, the totem pole connection seem off, the positive voltage is suppose to be at the collector of the npn transistor while the ground should be at the collector of the pnp, but it's in the other way round. Is this a mistake or it is intentional ?

Yes, the complementary emitter follower is reversed.

 

Yes, the complementary emitter follower is reversed.

Pls explain more, I don't understand what you mean

 

Also, I want to assume that the circuit will not be able to handle more than 30v output, this is because the 3845 IC max input voltage is 30v, anything above this will fry the IC. Am I correct?

 

Just for grins and giggles, I decided to simulate your power stage, and it certainly does not look like it was designed but rather thrown together like a patchwork quilt. In particular with a 15% duty cycle we get approximately 13.53V output from 150V input. We should be getting 22.50 out for that duty cycle. Other choices of nominal duty cycle produce the same subpar result. We also note that for low output currents determined by the LED and the 332Ω we are unable to remain in continuous conduction mode (CCM) as you can see from the current in I(L1). The results are similar for other fixed loads. The jump you see in tha amplitude of V(m1s) is actually ringing at the turn off. That ringing does not occur until V(out) gets close to its maximum valu and the current ripple reduces to a very low value

I think you might want to get the power stage operating in CCM at reasonable load currents before fooling around with anything else. Maybe I just missed something, and I don't actually understand what you are trying to do. Even if that is the case this power stage has problems that should be addressed.

Q: What switching frequency were you planning to use? That is an integral part of selecting the inductor and the capacitors.

 

I am trying to design a simple buck converter that will accept input of upto 150V and output 15V

What current output for the 15V?

 

This is the LInkswitch datasheet.
https://www.power.com/sites/default/files/documents/linkswitch-tn2_family_datasheet.pdf
The circuit labelled "high side buck direct feedback" is the same principle.

 

Just for grins and giggles, I decided to simulate your power stage, and it certainly does not look like it was designed but rather thrown together like a patchwork quilt. In particular with a 15% duty cycle we get approximately 13.53V output from 150V input. We should be getting 22.50 out for that duty cycle. Other choices of nominal duty cycle produce the same subpar result. We also note that for low output currents determined by the LED and the 332Ω we are unable to remain in continuous conduction mode (CCM) as you can see from the current in I(L1). The results are similar for other fixed loads. The jump you see in tha amplitude of V(m1s) is actually ringing at the turn off. That ringing does not occur until V(out) gets close to its maximum valu and the current ripple reduces to a very low value
View attachment 329355
I think you might want to get the power stage operating in CCM at reasonable load currents before fooling around with anything else. Maybe I just missed something, and I don't actually understand what you are trying to do. Even if that is the case this power stage has problems that should be addressed.

Q: What switching frequency were you planning to use? That is an integral part of selecting the inductor and the capacitors.

Thanks for the simulation. I am planing to use 80kHz

 

What current output for the 15V?

Minimum of 20A

 

Here is an updated simulation, using your specifications for computing an inductor value and a capacitor value. The simulation uses ideal components without any parasitic elements for the inductor and capacitor. The idea is to get things into the ballpark so you can add refinements going forward.


You can see from the measurements we exceeded the design efficiency at 88% and came close to the design current ripple a 2.2 Amperes, but we missed the voltage ripple at 3.3%. To get meaningful results for our measurements, we need to skip the startup phase where the input supply is ramping up.

 

Here is an updated simulation, using your specifications for computing an inductor value and a capacitor value. The simulation uses ideal components without any parasitic elements for the inductor and capacitor. The idea is to get things into the ballpark so you can add refinements going forward.
View attachment 329408
View attachment 329409
You can see from the measurements we exceeded the design efficiency at 88% and came close to the design current ripple a 2.2 Amperes, but we missed the voltage ripple at 3.3%. To get meaningful results for our measurements, we need to skip the startup phase where the input supply is ramping up.

Thanks for the simulation, it helps