drjohsmith
- Joined Dec 13, 2021
- 1,615
The interpreter is not limiting the ADC speed,@crutschow
using a shunt wont eliminate my delay problem as i cant sample simultaneously with the onboard adc's , i still need a deay to compensate for the read time difference of about 100uS as mentioned
@michael8
thats what im leaning toward using s/h with a programmable delay for the holdoff
@Ian
params all previously discussed as well as the mcu etc, no delay gives >70% error @20khz, delay to within 400nS of perfect sync gives 5% error, and obviously a tighter match improves this. the highest freq gives worst error. looking for at least 5% accuracy hopefully better
@Dr
yes sampling continously @ 5ish ksps and storing then averaging and processing after the sample buffer is full, as i said nyquist doesnt matter as this is a long term ave , ive already tested it and its accurate for freq even higher than the 20k target. im not needing 1 cycle resolution so the averaging over tens of thousands of cycles is accurate for repetitive waveforms. the adc is rated at 1msps so is plenty faster enough, reason for it being so slow is the circuitpython interpreter for the code on the M4 samd51 microcontroller is neutering the hardware , but its what i have to work with and try to work around
you "just" need to find out how to access the ADC directly , and allow it to DMA into RAM,
then you can use 50 KHz,
If your sampling at 5 Ksps,
and your averaging,
then no mater what , are not measuring "power" of the higher frequencies,
When you say
" ive already tested it and its accurate for freq even higher than the 20k target"
what test have you done ?
Averaging is a low pass filter,
https://www.analog.com/media/en/technical-documentation/dsp-book/dsp_book_Ch15.pdf
so again the higher frequencies power is lost,