Hello I am trying to implement the circuit bellow.
as i see it there is no way to supply both DC and AC on a simple 1 substrate 2 metal layer device because the RC connected to the opamps.
So i cannot connect -Vs and +Vs on the same layer, so i will do a VIA to M3 and draw there a trance and then another VIA from M3 to M1 +VS node.
but the M3 power supply layer also needs a ground, so should i use M4 as the ground for M3 and connect M4 and M2 grounds together with a VIA?
Does that makes any logical pcb design sense? or is there other alternative?
Thanks.

 

no idea what you mean by "both AC and DC"
and (not that i would do so) but why would one not be able to fit everything on one layer?
normally i run power rails side by side and under the ICs. after power (incl decoupling) is done, other signals are connected.
when all is done, ground zone can be used to fill the rest - go crazy on vias there.

so your U1 and U2 could be powered like this

 

https://www.allaboutcircuits.com/technical-articles/common-layer-stack-ups-for-a-four-layer-board/

 

Remember you can run traces under a component.

You need to have the physical layout of the parts and arrange them such as to minimize trace length and trace crossovers.
Then use the schematic to make the connections.

You can't properly do a layout from just the schematic.

 

Hello ,I think that if we put power rails and the RC traces on one layer .
they will intersect.
Where my logic is wrong? even if the traces would be under the componenet they will still intersect the RC loop connection.
so as i see it they cannot xist on a single layer.
Where did i go worng?
Thanks.

 

even if the traces would be under the componenet they will still intersect the RC loop connection

Why do you think that's a problem?
It's not.

 

its a problem because they will intersect and AC current that is supposed to go to RC will partially go to the OPAMP bias DC supply

 

I make 1-layer boards all the time. Most need a few jumpers. for short jumps, I use 0Ω resistors.

 

The two traces can go under the R and C as well, especially if they are through hole. You must not be communicating the problem very well.

 

yes i understand my error.
Thank you very much.

 

if you are planning to make a PCB for this, you better consider few things like adding some bypass caps and making things really small. by the looks of the parts (1pF caps and high speed opamps) it looks like this may be intended for high frequency operation. you may want to try different part placement and routes to find better one. for inspiration, here is a quick and dirty draft using 2 layer board. all traces are on top, bottom layer is just ground plane. here R and C size is 0603.

 

Hello Panic mode, I want to use a 10n and 1uF capacitors for decoupling as shown bellow is it ok to connect them like in the photo below?
I know they need to be as close as possible to the opamp chip.
I know that they needs to be ceramic and low esr.
There is 1uF ceramic capacitor shown in the link below, but i am not sure if it has low ESR?
the circuit tranfer function is 0 to 2MHz.
is there a way i could know withougt guessing what decoupling capacitorvalue i need to use?
Thanks.


https://media.digikey.com/pdf/Data Sheets/Samsung PDFs/CL05A105KP5NNN_Specsheet (1).pdf

 

its a problem because they will intersect and AC current that is supposed to go to RC will partially go to the OPAMP bias DC supply

No, it won't.

There will be a teeny tiny amount of capacitive coupling between the power traces and the current path through the inside of the R and C. This will be trivial compared to the signal current.

If your circuit had signals in the MHz range, of very high speed square waves, then there could be some noise coupling. None of that applies to your application.

ak