glitches of switched-capacitor circuits

Discussion in 'Analog & Mixed-Signal Design' started by Chandler Timm Doloriel, Apr 11, 2018.

  1. Chandler Timm Doloriel

    Thread Starter New Member

    Apr 5, 2018
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    0
    what are the switched capacitor glitches that can be solved by making a good clock generator.

    I have a clock generator made and its application is to test the clocks to a switched capacitor, what are the parameters that i should look for if I'm aiming to solve those glitches using my clock generator.

    My clock Generator frequency is 32kHz. what kingd of switched capacitor I can use for this?

    Also if you can provide or tell some full research paper regarding my matter, it would be very helpful.
     
  2. danadak

    Well-Known Member

    Mar 10, 2018
    1,435
    293
    Are you trying to do filtering with switch cap technology ? If so what
    switch cap part are you using ?

    If filtering what are the specs/description of the filter you are trying to create ?

    Regards, Dana.
     
  3. Chandler Timm Doloriel

    Thread Starter New Member

    Apr 5, 2018
    29
    0
    As of now I'm using a simple transmission gate and capacitor switched cap. Any simple switched cap is okay, I'm not particular with switched cap as long as I calculate the results wrt to my clock gen, it is okay
     
  4. crutschow

    Expert

    Mar 14, 2008
    19,518
    5,443
    There are two types of glitches that can occur in switched-capacitor circuits.

    One is feedthrough due to the gate-source and gate-drain capacitance. The feedthrough spike voltage from this can be reduced by reducing the clock rise and fall times, but the total charge transferred to the channel does not change. Thus you want to use a transmission gate with low gate capacitance, and with the p-channel and n-channel having their capacitances matched as close as possible.

    The other glitch can occur if the edges of the two-phase clocks used in a typical switched-capacitor processing circuit overlap. For that you need to generate a non-overlapping two-phase clock.
     
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