Getting started with a "sample and hold" circuit

Thread Starter

Tomoms

Joined Feb 3, 2020
3
Good morning guys, this is my first post here. I have to prepare a project for a university exam and I'd like to build a "sample and hold" circuit. I'm almost a total newbie in this field (I've only studied this stuff on books, never did anything practical), so I did some research and came up with some links:
http://www.emagtech.com/wiki/index.php/Advanced_Tutorial_Lesson_11:_Designing_Sample-And-Hold_Circuits#Building_an_Op-Amp_Sample-And-Hold_Circuit
https://www.electronicshub.org/sample-and-hold-circuit/

The first one looks promising, it shows the expected result after simulating the circuit using a computer (PSpice perhaps?) and that's what I'd like to build. However I've got a few of questions about the feasibility of this idea.
1) That website says I must use 2 AD711 op-amps, but I only have access to the classical 741 op-amp. Would the circuit still work with those?
2) I've read somewhere else (perhaps in the second link I've listed) that the capacitor must be electrolytic, in order for the leakage current to be small. Now, I barely know what a leakage current is, but the actual question is: would a ceramic capacitor work? Because I've asked the guy who runs my university's electronics lab to give me a 1 nF capacitor and he gave me a ceramic one. I'll have to check if he's got an electrolytic one, if it's strictly needed.
3) How the hell do I generate the control voltage (VCTRL in the second link), which should be a square wave, if I'm not wrong? I was thinking of using an Arduino board (not sure about how to do it, but it should be doable), but would it work?
I mean, the goal is that I connect an oscilloscope to the input and the output of the circuit and I'd like to see something similar to this: http://www.emagtech.com/wiki/index.php/File:MixTUT4_12.png

Do you think it's possible to do what I want, given these conditions?
Thanks in advance for your help!

P.S. I'll surely come up with more questions later, this is it for now. Thanks!
 

danadak

Joined Mar 10, 2018
3,886
1) Yes, but compromised performance. The input bias current of AD711 <<<< 741,
so when J1 is off the hold cap will discharge due to bias current much more rapidly
in case of 741. This is called "droop". Also allowed input common mode range different.

I would advise you try to get either OpAmps with JFET or MOSFET inputs. Note 741 was
originally done with bipolar inputs, if you have a cmos version that would be just fine.


2) Ceramic caps potentially much less leakage than electrolytics. Polymer, Teflon
ultra low leakage, best for this application.

https://www.murata.com/en-us/support/faqs/products/capacitor/mlcc/char/0039


3) Vc must be able to turn on and off J1 under worst case conditions. This is signal
dependent given source is connected to OpAmp output. That in input signal.

For JFET operation, say a J108 - http://vakits.com/sites/default/files/J108.pdf

Look at specs for turn off and on, and graphs on Vgs vs Id characteristics.

https://www.electronics-tutorial.net/analog-integrated-circuits/sample-hold-circuit/

A series R between 2'ond OpAmp input and capacitor advised. Say 1 K ohms. To
minimize OpAmp input damage when sampling cap charged and power to OpAmps
turned off which can result in large discharge cap current flowing into / out of OpAmp
input. Degrading its input device characteristics.



Regards, Dana.
 
Last edited:

Delta prime

Joined Nov 15, 2019
161
sampleAndHold.jpeg
Easy peasy go ahead use your 741 or two sorry about that. Bust out the 741 datasheet and you're on your way you can choose your supply voltage and input waveform. You can also go digital no problemo. The schematic symbol for that capacitor is non polarized you can throw in polarized if you'd like ,your electrolytic,play around with different value capacitors.
 

crutschow

Joined Mar 14, 2008
24,318
I've read somewhere else (perhaps in the second link I've listed) that the capacitor must be electrolytic, in order for the leakage current to be small.
That's backwards.
Electrolytics have the highest leakage of any of the common capacitor types.
How the hell do I generate the control voltage (VCTRL in the second link), which should be a square wave, if I'm not wrong?
You could contact hell and generate that with a 555 timer IC configured as an astable oscillator.

A square-wave would work, but you may want it to go for a shorter period for the sample portion of the signal.
For example, your first reference shows the following signal parameters:
Note that the sample time is only 5us whereas the pulse period is 50us.
This can be done by changing the duty-cycle of the 555 astable circuit.
1580773930923.png
 

Thread Starter

Tomoms

Joined Feb 3, 2020
3
1) Yes, but compromised performance. The input bias current of AD711 <<<< 741,
so when J1 is off the hold cap will discharge due to bias current much more rapidly
in case of 741. This is called "droop". Also allowed input common mode range different.

I would advise you try to get either OpAmps with JFET or MOSFET inputs. Note 741 was
originally done with bipolar inputs, if you have a cmos version that would be just fine.


2) Ceramic caps potentially much less leakage than electrolytics. Polymer, Teflon
ultra low leakage, best for this application.

https://www.murata.com/en-us/support/faqs/products/capacitor/mlcc/char/0039


3) Vc must be able to turn on and off J1 under worst case conditions. This is signal
dependent given source is connected to OpAmp output. That in input signal.

For JFET operation, say a J108 - http://vakits.com/sites/default/files/J108.pdf

Look at specs for turn off and on, and graphs on Vgs vs Id characteristics.

https://www.electronics-tutorial.net/analog-integrated-circuits/sample-hold-circuit/

A series R between 2'ond OpAmp input and capacitor advised. Say 1 K ohms. To
minimize OpAmp input damage when sampling cap charged and power to OpAmps
turned off which can result in large discharge cap current flowing into / out of OpAmp
input. Degrading its input device characteristics.



Regards, Dana.
I guess I'll use the 741 anyway, I don't need great performance after all.
About the control voltage: that 'worst case' thing means that I have to ensure my square wave would generate an appropriate Vgs > Vt (Vt is the Vgs threshold after which the transistor starts conducting) during all the period of oscillation of the input sine wave, right? And can I use a BS170 MOSFET instead of a JFET? A BS170 has got Vt = 2 V, so e.g., if my input is sin(ωt) (semi-amplitude of 1), a square wave varying between 0 V and 4 V would be good, right?
Easy peasy go ahead use your 741 or two sorry about that. Bust out the 741 datasheet and you're on your way you can choose your supply voltage and input waveform. You can also go digital no problemo. The schematic symbol for that capacitor is non polarized you can throw in polarized if you'd like ,your electrolytic,play around with different value capacitors.
I don't understand what you mean with "you can also go digital". Could you explain, please?

You could contact hell and generate that with a 555 timer IC configured as an astable oscillator.

A square-wave would work, but you may want it to go for a shorter period for the sample portion of the signal.
For example, your first reference shows the following signal parameters:
Note that the sample time is only 5us whereas the pulse period is 50us.
This can be done by changing the duty-cycle of the 555 astable circuit.
Ok, I understand that, but what's the downside of having a square wave with half period dedicated to sampling and half period to holding? Only the presence of big "holes" between the samples? Because that would be totally acceptable for me. As I've said, this circuit should be just a simple demonstration, it isn't required that it performs flawlessly etc.

Thank you, folks!
 

crutschow

Joined Mar 14, 2008
24,318
what's the downside of having a square wave with half period dedicated to sampling and half period to holding?
The downside is that the output will be tracking the signal when sampling so may vary during the sample period.
If that's not a problem, then a square-wave is okay.
 

OBW0549

Joined Mar 2, 2015
3,204
And can I use a BS170 MOSFET instead of a JFET?
Not a good idea. MOSFETs have what's called the "body diode" which appears as a diode between drain and source, and conducts when the drain voltage and source voltage are reversed from the normal polarity.

You need to use a JFET or a MOS analog switch.
 

Thread Starter

Tomoms

Joined Feb 3, 2020
3
The downside is that the output will be tracking the signal when sampling so may vary during the sample period.
If that's not a problem, then a square-wave is okay.
That's not a problem. Do you think using an Arduino is a good way of producing such square wave?

Not a good idea. MOSFETs have what's called the "body diode" which appears as a diode between drain and source, and conducts when the drain voltage and source voltage are reversed from the normal polarity.

You need to use a JFET or a MOS analog switch.
Didn't know this, thanks. I'll try with a JFET.
 

crutschow

Joined Mar 14, 2008
24,318
Do you think using an Arduino is a good way of producing such square wave?
You could certainly use one for that purpose, depending upon the frequency wanted.
A 555 timer configured as an astable is also quite simple and requires no programming.
Your choice.
 

danadak

Joined Mar 10, 2018
3,886
For future reference, not this design. Very little coding, maybe just 4 lines of code
to start the individual components. You drag and drop components out of the
chips component catalog (attached), wire them up to internals and to pins, start
them with a line of code, your are done.

There are alternative ways to discrete designs these days.

This is a single chip that has both analog and digital functionality, from simple gates
to counters/timers/pwm, from simple OpAmps to references and SAR ADC and DelSig
ADC to DAC to even S/H and T/H and mixers.

If you look at top section this is a simple S/H using the onchip S/H component. A component
in PSOC is an onchip resource.

The constraints of the design are the sampling cap is fixed (its internal). In fact thats the reason
for showing the bottom solution as well, more like your design.

For both designs, since PSOC is single supply, to handle negative swing signals a divider
to Vref is used for an offset. That limits input Z primary downside. And affects accuracy
depending on what you use as Vref. You can use onchip Vref, send that out to a pin thru
onchip OpAmp buffer to handle that problem.

The PWM develops a one shot sample waveform, that if you wanted could be triggered
with other qualifiers, like V in a system, or T/Freq or whatever.

As you can see very little chip resources used, right hand window.


1580860713180.png

The boards is $ 10 for dev, https://www.cypress.com/documentation/development-kitsboards/cy8ckit-059-psoc-5lp-prototyping-kit-onboard-programmer-and

The IDE and Compiler free - https://www.cypress.com/products/psoc-creator-integrated-design-environment-ide

And you want to get real fancy you use the ARM core in the device and code for
much greater functionality.

If interested I have a tool to compute the input R divider for planning
offsets and signal swings and scaling for input.


Regards, Dana.
 

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