Generating gate signals for active clamp flyback

Thread Starter

SiCEngineer

Joined May 22, 2019
299
What is the best way to generate gate signals for the active clamp flyback, to ensure they never conduct at the same time?

I believe one would start with detecting the falling edge of the main switch gate signal, and at this point a timer counts a certain delay period, before sending a signal to the clamp switch. But I am struggling to think of the most efficient way to do this with electronics.

As a bonus, I am detecting the voltage on the FET VDS waveform. I plan to incorporate some kind of variable dead-time approach to optimise the efficiency of the converter.

Does anyone know of any circuits which could perform this function?
 
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