Something like this.
Then invert either A or B to get a complimentary output.

View attachment 254343

when you invert either A or B, lets say A itll always stay high even when not pwming that signal. how can one turn it off to ensure it doesnt stay high. i am having a hard time with this thanks.

Mod: link to old Thread
https://forum.allaboutcircuits.com/...entary-pwm-with-dead-time.183546/post-1689230

 

Don't existing chips like the SG3524 do this for you?
https://www.ti.com/lit/ds/symlink/s...33943&ref_url=https%3A%2F%2Fwww.google.com%2F

 

Why do you need to?
what is connected to the output of the half-bridge?

 

If you really need both outputs low, then connect the spare AND-gate in series with the high output.
Applying a low signal to one of the inputs will keep the output low.
Applying a high signal to that input will allow the output to toggle from the input signal.

 

If you really need both outputs low, then connect the spare AND-gate in series with the high output.
Applying a low signal to one of the inputs will keep the output low.
Applying a high signal to that input will allow the output to toggle from the input signal.

if I do this, it'll and both and I won't get the output from A

 

if I do this, it'll and both and I won't get the output from A

like I won't get the output I need when I pwm.

 

The AND-gate signal will need to be separate from the clock signal.
It needs to go low when the clock stops.

 

I also agree with Dick.
There are several chips that would do exactly what you require.
With the 3525 being ubiquitous.

 

I also agree with Dick.
There are several chips that would do exactly what you require.
With the 3525 being ubiquitous.

Thanks, is there an LT spice model for this ic?

 

I also agree with Dick.
There are several chips that would do exactly what you require.
With the 3525 being ubiquitous.

Really nice chips but they’re limited by their duty cycle. I need to be able to operate to about 80%.

 

Really nice chips but they’re limited by their duty cycle. I need to be able to operate to about 80%.

So what’s connected to the output of the half bridge?

 

So what’s connected to the output of the half bridge?

I am driving a dc brushed motor. I have the dgd2190m gate driver on my power mosfets. It’s an all 4 n-channel mosfet h bridge, each mosfet has a Qg of 268nC. My plan was to set up the pwm controller before the gate drivers.

 

I am driving a dc brushed motor. I have the dgd2190m gate driver on my power mosfets. It’s an all 4 n-channel mosfet h bridge, each mosfet has a Qg of 268nC. My plan was to set up the pwm controller before the gate drivers.

Is there any situation when the motor must be able to freewheel? i.e. the output shaft can be turned by the load?
If not, then it is an advantage if both lower FETs are switched on, as it will prevent the motor from rotating when it is not required to move.

 

Is there any situation when the motor must be able to freewheel? i.e. the output shaft can be turned by the load?
If not, then it is an advantage if both lower FETs are switched on, as it will prevent the motor from rotating when it is not required to move.

The main issue I am having is that with my dead time circuit, even when I am not pulsing , the output that’s inverted remains high and while I am operating in the opposite direction that means both lower fets are on and I am seeing an insane amount of power dissipation when Ieave it like that.

 

The main issue I am having is that with my dead time circuit, even when I am not pulsing , the output that’s inverted remains high and while I am operating in the opposite direction that means both lower fets are on and I am seeing an insane amount of power dissipation when Ieave it like that.

Something else must be wrong. If the two lower FETs are on, then both sides of the motor are connected to 0V and there is no current path from the supply.

 

Something else must be wrong. If the two lower FETs are on, then both sides of the motor are connected to 0V and there is no current path from the supply.

If both lower fets are on am I not creating a path straight to ground on 1 side? Hence shorting the supple?

 

If both lower fets are on am I not creating a path straight to ground on 1 side? Hence shorting the supple?

I am just very confused because I keep seeing the same dead time circuit online but when you invert 1 side it stays on indefinitely.

 

If both lower fets are on am I not creating a path straight to ground on 1 side? Hence shorting the supple?

No - the drive to the upper FET is the inverse of the lower, so it will be OFF.

 

No - the drive to the upper FET is the inverse of the lower, so it will be OFF.

This is what i am referring to.



the above is not normal. that bottom signal should be 0, but because of the inverter it is sending the supply voltage. on the same side.

 

Did you mention a multiplexer way back a thousand posts ago? Or was that someone else?
You seem to have a clock and a PWM waveform, when you need a direction control and a PWM waveform.
The logic should look like this. Apply de Morgan’s laws and you can do it with all NOR gates, but you still need 5. Or alternatively, you can use a 74HC139 demultiplexer and a couple of inverters.
The dead-time networks come at the end, like you have them before.
However, I would recommend a half-bridge driver, especially and adaptive half bridge driver, as it will deal with the dead time for you.