I want to generate +20/-4 V after A1. Now the A1 output voltage level is 0/1.
Thank you.

 

This appears to be LTSPICE. You can set the voltage values of 1 and 0. I have set the 1 value to 3.3V or 5.0V or 12V I have not tried setting the 0 value to -4V.
There are good helps for LTSPICE.

 

hi EM,
Welcome to AAC.
Please post your LTSpice asc file.
E

 

hi EM,
Welcome to AAC.
Please post your LTSpice asc file.
E

Thank you for your help. The attachment is document.

 

Thank you for your help. The attachment is document.

I want use the document generate dead time in g1 and g2. But I used the rc circuit, the out put voltage is not right(A1). The A1 should be +20/-4v.

 

hi EM.
You have not set up the digital A1 AND gate Vcc.

This is what I see when using 74HC gate.
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Added: 20V/-4V plot

 

hi EM,
This is an example on how to set the digital Logic Vhigh/low.
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hi EM,
This is an example on how to set the digital Logic Vhigh/low.
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View attachment 343247

I used this method, but the g1 and g2 dead time miss right area. Do you have some suggestions?

 

I used this method, but the g1 and g2 dead time miss right area. Do you have some suggestions?

I used your mention method, but the g1 and g2 dead time is asymmetric. How can you change it?

 

I used your mention method, but the g1 and g2 dead time is asymmetric. How can you change it?

It appears that you are trying to construct a circuit that has a very specific behavior, but doing so by tweaking simulation parameters to get the models to produce the results in the computer that you want. But if you want to then construct a physical circuit that behaves the way you want, you need to do it the other way around. Get the models tweaked so that the simulation results match their actual behaviors and then construct a circuit that, using those reality-based models, does what you need. At that point, you have a fighting chance that the physical circuit will be reasonable close to the simulation results.

 

All these years of using LTSpice, and I wasn’t aware that one could set Vhigh and Vlow, thanks W!!

 

hi EM,
The g1 and g2 waveform plots on my simulation are overlapped OK.

BTW: when you post a plot, please add label names to your Nodes, it make it easier to identify on the circuit.
E

 

hi EM,
The g1 and g2 waveform plots on my simulation are overlapped OK.

BTW: when you post a plot, please add label names to your Nodes, it make it easier to identify on the circuit.
E
View attachment 343287

Thank you for your help.
I solved this problem. I came across a new problem. Can the half-bridge inverter produce a three-level output? I think not.