Hi all,

I am looking to create a circuit that takes as input a 0V-1.5V variable frequency square wave with a 50% duty cycle and outputs a square wave of the exact same amplitude, duty cycle and frequency but with a lower limit of 85Hz. Once the input frequency drops below 85Hz the output frequency should stay at 85Hz, 50% duty cycle and the amplitude should stay 0V-1.5V.

The transition from variable to fixed frequency at the 85Hz corner should be 100% seamless, with absolutely no changes in the duty cycle or even a single mark/space period.

The upper limit of the frequency need not be any more than 2.5kHz.

I am not necessarily looking for a complete or even partial design, although this would be appreciated.
Any ideas or component recommendations to point me in a design direction should suffice.

FWIW: This can be done in a heartbeat with any decent microcontroller, CPLD or FPGA but the design brief prohibits the use of these.

Thanks in advance.

 

Maybe a Phase Locked Loop with the lower VCO frequency limit set to 85 Hz.

Going down in frequency is relatively simple, but what happens when the frequency increases through 85 Hz?
There is always going to be a phase difference that needs to be reconciled.

 

Thanks for your reply Sensacell.

You're absolutely correct. The phase difference is the major burning point in this design. We've considered a VCO based design but the phase shift keeps coming back to haunt us.

Regards

 

Maybe a Phase Locked Loop with the lower VCO frequency limit set to 85 Hz.

Going down in frequency is relatively simple, but what happens when the frequency increases through 85 Hz?
There is always going to be a phase difference that needs to be reconciled.

And the output amplitude needs to be matched to the input and this is non-trivial especially as the TS spec includes that the input square wave is allowed to go down to zero volts.

 

Hi AlbertHall

Correct - the input frequency is allowed to reduce to zero volts.

All the while the output remains steady at 85Hz, 50%, 0V-1.5V.

Regards

 

Thinking about this again - there is no specific requirement for the input and output signals to be in phase.

They merely need to be of the same frequency, amplitude and duty cycle.

 

And the output amplitude needs to be matched to the input and this is non-trivial especially as the TS spec includes that the input square wave is allowed to go down to zero volts.

That detail escaped me.
Is there some other reference signal? how can the input signal go to zero volts and yet be processed by a subsequent circuit?
Assuming a reasonable lower threshold, I can imagine a peak detector circuit that is reset every cycle, the output gets gated by the processed digital signal.

This is a bitch - explain the larger context of the problem?

 

That detail escaped me.
Is there some other reference signal? how can the input signal go to zero volts and yet be processed by a subsequent circuit?
Assuming a reasonable lower threshold, I can imagine a peak detector circuit that is reset every cycle, the output gets gated by the processed digital signal.

This is a bitch - explain the larger context of the problem?

Thanks for your reply Sensacell

Here's the context of the problem: We have an electric motor driving a gearbox. An electronic drive circuit increases motor RPM when a reluctor sensor on the final drive of the gearbox outputs a frequency < 85Hz.

We need to implement a circuit that prevents this from happening when a switch in the control room is turned on by fooling the drive circuit into thinking the sensor is still going at 85Hz.

In practical terms the motor will gradually decline to 0 RPM for around 1-6 seconds. There's a safe mechanical slippage mechanism in place to ensure no damage, but during this period we don't want the drive to increase power to the motor.

The problem is that the drive unit is very sensitive to abrupt changes in mark/space ratio, and when it detects this, it assumes a faulty reluctor sensor and shuts down the motor.

 

A 4046 PLL using the type II (digital) phase detector may work, except for duty-cycle.
When the input frequency goes below the minimum VCO frequency it should just stay at that frequency.
And the phase-shift stays very near zero over the whole lock range.

But the output duty-cycle will stay at 50% I believe, independent of the input duty-cycle.

Here's a discussion of the 4046.
Below is an excerpt discussing the Type II phase comparator.