So in the diagram, the 3rd and 4th stage outputs of the J Ks are going to a Nand gate then back to CLR... these would be 4 and 8 of 1 2 4 and 8 = 12 would I do the same concept for Mod 9 and Mod 13..meaning outputs from 1st and 4th stage 1 and 8 = 9 going to Nand gates and back to CLR.....same with 13 1st 3rd and 4th stage = 1 4 and 8 = 13
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