Flyback reflected voltage in this circuit

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Blue_Electronx

Joined Jun 10, 2019
112
Hello,

I'm looking into this reference design: http://www.ti.com/lit/df/tidrlf7/tidrlf7.pdf . See it attached also.

I have three questions:

1) What could be the reflected voltage? I see D1 is 110V, so it leads me to think they chose a low reflected voltage for this wide input range (64-1260VDC). This is what I think:

With two 800 V mosfets, we should leave at least 100V safety margin when at max voltage. So, we don’t want to exceed 700V on each drain, i.e., in total 1.4kV.

Vinmax + Vz = 1400 + Vz <=1200

Vz <=1400 – 1200 = 200V

Let’s pick Vz = 110V

Vz/VOR = 1.4 optimum ratio

VOR =0.7*110 = 77 Is this Okay?

2) How is the voltage shared between the two transistors? Is there a moment when a transistor could get more stress than the other?

3) They don't use bulky capacitors at the rectifier output. Is not ripple an issue then?
 

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