I came across this circuit in a TI design guide for a MPPT charge controller (https://www.ti.com/lit/ug/tiduej8a/tiduej8a.pdf):
It says it's for "voltage sense of floating panels (disconnected via low-side panel enable)." I'm having trouble understanding how it's supposed to work when there's no DC connection between ground and the panel low side (P-). The full schematic of the design is here: https://www.ti.com/lit/pdf/tidryu8 and here is the section showing the panel connection:
How is the measurement circuit going to produce a current from P+ to ground when there's no DC connection between P- and ground? I tried simulating the measurement circuit along with the high value capacitors and a load resistor to ground in place of the controller circuits that are powered by the panel:
The simulation showed a large current from the source, through the large capacitance (charge transfer), and through the FET's source-drain diode to return to the source. This enabled a current through the PNP of the voltage measurement circuit, but it was much too high and resulted in saturation of the PNP with a 12V collector voltage, whereas the document says it should be less than 3.3V for the MCU ADC.
They state this circuit is supposed to enable voltage measurement of the panel when the low side is disconnected from ground, but I don't see how that could be so when the source (panel) and measurement circuit don't share a ground. Any thoughts?
It says it's for "voltage sense of floating panels (disconnected via low-side panel enable)." I'm having trouble understanding how it's supposed to work when there's no DC connection between ground and the panel low side (P-). The full schematic of the design is here: https://www.ti.com/lit/pdf/tidryu8 and here is the section showing the panel connection:
How is the measurement circuit going to produce a current from P+ to ground when there's no DC connection between P- and ground? I tried simulating the measurement circuit along with the high value capacitors and a load resistor to ground in place of the controller circuits that are powered by the panel:
The simulation showed a large current from the source, through the large capacitance (charge transfer), and through the FET's source-drain diode to return to the source. This enabled a current through the PNP of the voltage measurement circuit, but it was much too high and resulted in saturation of the PNP with a 12V collector voltage, whereas the document says it should be less than 3.3V for the MCU ADC.
They state this circuit is supposed to enable voltage measurement of the panel when the low side is disconnected from ground, but I don't see how that could be so when the source (panel) and measurement circuit don't share a ground. Any thoughts?