Hey, I have a basic question that I haven't been able to found anywhere, not even in the flip flop datasheet (IC4013 btw). I'm going to build a guitar pedal that produces a signal a octave lower from the input, and then pass it through filters to get it more clean, or less dirty. The thing is, from which input voltage does the flip flop consider a 1?

 

Keep in mind that a digital IC does not pass amplitude variations from its input to its output. Whatever shows up on the Clock pin, the output will be a square wave if the input is loud enough, or nothing if it isn't. So no matter how much signal filtering you do before the 4013, it is going to have a serious fuzz effect after. Also, small amplitude variations caused by harmonics will be lost. Dividing audio with a digital circuit is nothing like running the audio through either a hetrodyne circuit or a balanced mixer to shift its bandwidth.

If you're ok with all of that, a 4013 has two halves. Each half has clock, data, set, and reset inputs, and two complimentary outputs, Q and Q-. Connect Q- to the Data input, and drive the clock input with the audio. Tie the Set and Reset inputs to GND.either the Q or Q- output can be used to drive the downstream circuits. You will have to AC-couple the audio into the clock pin. For the unused half, tie *all* input pins to GND.

A better way, with one extra chip, is to run the audio through one section of a CD4093 quad NAND or CD40106 hex inverter. These gates have a Schmitt Trigger input stage, which will do a better job of turning the audio into a digital signal the 4013 wants to see. There are subtle reasons both for and against this.

ak

 

Keep in mind that a digital IC does not pass amplitude variations from its input to its output. Whatever shows up on the Clock pin, the output will be a square wave if the input is loud enough, or nothing if it isn't. So no matter how much signal filtering you do before the 4013, it is going to have a serious fuzz effect after. Also, small amplitude variations caused by harmonics will be lost. Dividing audio with a digital circuit is nothing like running the audio through either a hetrodyne circuit or a balanced mixer to shift its bandwidth.

If you're ok with all of that, a 4013 has two halves. Each half has clock, data, set, and reset inputs, and two complimentary outputs, Q and Q-. Connect Q- to the Data input, and drive the clock input with the audio. Tie the Set and Reset inputs to GND.either the Q or Q- output can be used to drive the downstream circuits. You will have to AC-couple the audio into the clock pin. For the unused half, tie *all* input pins to GND.

A better way, with one extra chip, is to run the audio through one section of a CD4093 quad NAND or CD40106 hex inverter. These gates have a Schmitt Trigger input stage, which will do a better job of turning the audio into a digital signal the 4013 wants to see. There are subtle reasons both for and against this.

ak

I'm aware of that, but since I'm not an expert I can't make a better and simpler solution. I will pass the output signal through a low pass filter to get it the cleanest possible. The thing is, what is the threshold of the flip flop, from what voltage will it consider a 1 and not a 0?

Also another question, after the filter the signal will be biased, in this case, passing through a capacitor will remove the bias?

Thanks for the answer.

 

I'm aware of that, but since I'm not an expert I can't make a better and simpler solution. I will pass the output signal through a low pass filter to get it the cleanest possible. The thing is, what is the threshold of the flip flop, from what voltage will it consider a 1 and not a 0?

Also another question, after the filter the signal will be biased, in this case, passing through a capacitor will remove the bias?

Thanks for the answer.

For CMOS logic, the threshold voltage is approximately half the supply voltage. Hence if you are running the flip-flop at 3V, the threshold is 1.5V.

 

I'm aware of that, but since I'm not an expert I can't make a better and simpler solution. I will pass the output signal through a low pass filter to get it the cleanest possible. The thing is, what is the threshold of the flip flop, from what voltage will it consider a 1 and not a 0?

Also another question, after the filter the signal will be biased, in this case, passing through a capacitor will remove the bias?

Thanks for the answer.

Hello,

This is a little tricky because what will happen is the logic will trigger when the amplitude is high enough, then start to cut out as the amplitude dies down, so the logic will start to be triggered partly by volume and partly by noise until the amplitude gets low enough where the noise no longer adds enough to the signal. This may sound very nasty.

What you might be able to do is use a gain controlled amplifier after the divider so that the output amplitude follows the input amplitude. As the input dies down, the output also dies down.

Yes a capacitor is used to remove the DC bias so the output is centered around 0v instead of some higher level like 2.5v DC. That's sometimes called a "blocking capacitor" or coupling capacitor.

 

For CMOS logic, the threshold voltage is approximately half the supply voltage. Hence if you are running the flip-flop at 3V, the threshold is 1.5V.

If I supply 3 V and -3V to the flip flop will the wave be centered in zero? Having 1.5 V as 1 and -1.5 V as a 0?

What you might be able to do is use a gain controlled amplifier after the divider so that the output amplitude follows the input amplitude. As the input dies down, the output also dies down.

Yes a capacitor is used to remove the DC bias so the output is centered around 0v instead of some higher level like 2.5v DC. That's sometimes called a "blocking capacitor" or coupling capacitor.

Hi, thanks for the answer, I tried doing that in multisim and it didn't remove the bias. I didn't understand what you meant by using the gain controlled amplifier to follow the input.

 

If your supply is 3V and -3V, the threshold voltage is 0V.
A voltage above 0V is logic 1, below 0V is logic 0.

 

If your supply is 3V and -3V, the threshold voltage is 0V.
A voltage above 0V is logic 1, below 0V is logic 0.

So there's no way I can get the wave centered at zero? I mean I could make a negative bias, using an op-amp to invert the dc source polarity.

Btw, what would be the voltage of logic 1 and logic 0? I suppose logic 0 would have 0 volts.

 

https://www.allaboutcircuits.com/textbook/digital/chpt-3/logic-signal-voltage-levels/

If you bias the CMOS to plus 3 and minus 3 the center will be zero, but the output center will depend on how well matched the high side drive is compared the low side drive and this partly depends on how the load is connected. If the load is resistive and connected to zero volts then it maybe nearly centered, but there will always be some small difference.

The CMOS thresholds are also subject to temperature and process variations. The best bet is to make sure the input is always overdriven so that it does not matter if the thresholds vary a little. This means larger amplification for the input of the logic even though the output may be reduced for the actual audio.

The idea is to make sure the CMOS always gets triggered, and to keep the output amplitude the same as the input amplitude unless of course you want to add sustain but that would be covered by another circuit function.
Just to note, it would be bad to try to obtain sustain by using the output of the FF directly without any signal conditioning.

 

So there's no way I can get the wave centered at zero? I mean I could make a negative bias, using an op-amp to invert the dc source polarity.

Put a capacitor in series with the signal followed by a pulldown resistor to GND.

Btw, what would be the voltage of logic 1 and logic 0? I suppose logic 0 would have 0 volts.

-3V to 0V is logic 0.
0V to 3V is logic 1.

Logic at 0V is undefined.

(Assuming the supply voltage is -3V and +3V, but I don't know why you would want to do this.)

 

Put a capacitor in series with the signal followed by a pulldown resistor to GND.

-3V to 0V is logic 0.
0V to 3V is logic 1.

Logic at 0V is undefined.

(Assuming the supply voltage is -3V and +3V, but I don't know why you would want to do this.)

I thought it would center the wave, since it won't there's no use for it. But what would come out of the flip flop? How many volts when it's 1 or 0?

That works, but I would need some tweaking around to get it centered, since for differente values of frequency, capacitance and resistance the bias would change.

 

I thought it would center the wave, since it won't there's no use for it. But what would come out of the flip flop? How many volts when it's 1 or 0?

That works, but I would need some tweaking around to get it centered, since for differente values of frequency, capacitance and resistance the bias would change.

Many guitar pedals are powered from a 9V/PP3 battery. Or you can use an AC-to-DC adapter.
If Vcc = 9V and GND = 0V, then the output of the CMOS flip-flop will be 0V for logic 0 and 9V for logic 1.