Hello,
The question here is to determine what logical function is implemented in this circuit above, which uses nMOS and pMOS transistors as active high and active low switches, respectively. I made the truth table, and found that for negative logic (0 is true), the function is OUT = ACD + ABC + ABCD. For all other combinations, the value of OUT would read logic high or VDD since there is no current path to ground, and there is always a path to VDD. I'm not sure if this is right because I am still learning about transistors. Since the transistor is really a four terminal device, the gate input connects to ground inside the device, while drain and source connect when the switch is on, but are physically identical. This would mean that the only way for the OUT to see high logic level is to have a current path to VDD, since the gate inputs would not connect to OUT. Drain and source are the "ends" of the switch which get connected when the transistor is "on." Is that a correct description of the transistor? Do you think the logical function I found is right?
Thanks,
J_Rod

 

The MOSFET is a four terminal device, if you include the substrate connection, but that is normally connected to the plus or minus (ground) depending upon the MOSFET polarity.

The gate input is not connected to ground in a MOSFET (where did you learn that?), it is only connected to the gate.

A MOSFET transistor is ON when the gate-source voltage exceeds its threshold value (positive for N-channel and negative for P-Channel).

 

The fourth terminal in a MOS transistor is the substrate and it forms parasitic diodes to the source/drain regions. It is normally connected to the source (or the appropriate supply in the case of an IC) in order to keep those parasitic diodes reverse biased.

The gate is capacitively coupled to the drain/source regions, but there is no DC connection to it.

The bridge between the outside lines below the A PFET serves no purpose since both of those signals are already connected directly to Vdd.

Why are you choosing to use negative logic? Is that required by the assignment?

CMOS ladders are generally drawn so as to emphasize the complementary nature of the configurations. In the NFET portion the A and C transistors are in series, so they should are in parallel in the PFET portion. While they are in parallel in your diagram, the way it is drawn obscures this.

Let's sanity check your answer:

OUT = ACD + ABC + ABCD

This means that the output is FALSE whenever A is FALSE. Because your are using negative logic, that means that the output is HI (false) whenever A is HI (false). Is that consistent with your circuit?

Let's go from the circuit. The output is HI whenever A is LO. That means that the output if FALSE whenever A is TRUE. Is that consistent with your answer?

Draw the truth table using H and L (High voltage and Low voltage). Remember, this is not a logic circuit it is merely a circuit with a bunch of transistors and, at the end of the day, it neither knows nor cares about what you choose to call a TRUE and a FALSE, it only knows voltage levels.

Once you have the truth table using H and L, go in and replace H with F (or 0) and L with T (or 1) and then determine the Boolean expression for the logic function that is implemented.

 

Thanks for the replies. Is it correct then to say that there are no DC connections inside the transistor, aside from metal contacts on the outside, because the energy transfer happens between the atoms themselves, similar to a parallel plate capacitor?

CMOS ladders are generally drawn so as to emphasize the complementary nature of the configurations. In the NFET portion the A and C transistors are in series, so they should are in parallel in the PFET portion. While they are in parallel in your diagram, the way it is drawn obscures this.

I noticed this on the NAND and NOR gate construction using nMOS and pMOS transistors, because they were drawn to emphasize that complementarity.

This means that the output is FALSE whenever A is FALSE. Because your are using negative logic, that means that the output is HI (false) whenever A is HI (false). Is that consistent with your circuit?

It would not be consistent because if A and C and D were HI voltage level, there would be a path for current flow to the OUT node. I got confused with negative logic and thought that the Boolean expression found (OUT = ACD +ABC +ABCD) would show when the output is LOW.

I rewrote the truth table like you said and made the Karnaugh map. I found OUT = C' +A'C +D'B'. That is, OUT is HI voltage whenever C is LOW, or when A is LOW and C is HI, or whenever D and B are LOW. Do you think that is right?

 

Thanks for the replies. Is it correct then to say that there are no DC connections inside the transistor, aside from metal contacts on the outside, because the energy transfer happens between the atoms themselves, similar to a parallel plate capacitor?

No, it is not correct to say that. The gate voltage (relative to the source/drain regions) produces an electric field that creates a channel underneath the gate region that permits charge carriers to flow between the source and drain terminals.

I noticed this on the NAND and NOR gate construction using nMOS and pMOS transistors, because they were drawn to emphasize that complementarity.

And that emphasis is a good thing because it helps to communicate the structure and function of the circuit.

It would not be consistent because if A and C and D were HI voltage level, there would be a path for current flow to the OUT node. I got confused with negative logic and thought that the Boolean expression found (OUT = ACD +ABC +ABCD) would show when the output is LOW.

I'm not quite sure how to interpret the last part of your sentence. If you are using negative logic for both the input and output signals, then you DO want your expression for OUT to be TRUE when OUT is LO. The point is that this expression fails that test. If A is LO (a low voltage but a TRUE logic level), then the output is HI (a high voltage but a FALSE logic level) regardless of the state of the other signals. But this expression does not reflect that since if A is TRUE, whether the output is TRUE or FALSE depends on the other signals.

I rewrote the truth table like you said and made the Karnaugh map. I found OUT = C' +A'C +D'B'. That is, OUT is HI voltage whenever C is LOW, or when A is LOW and C is HI, or whenever D and B are LOW. Do you think that is right?

Probably not, because you are talking about the signals using the wrong terms. A Boolean expression knows nothing about HI and LO, it only knows about TRUE and FALSE.

Your expression says that OUT is TRUE any time that C is FALSE. Using negative logic, that means that OUT is LO whenever C is HI. Is that the case?

Instead of saying that you rewrote the truth table, how about posting the truth table so that we can see what you did right and what you did wrong. Don't make us read your mind or break out our crystal balls.

 

Using HI (H) voltage for logical 1 or TRUE, and using LOW (L) voltage for logical 0 or false,



the Boolean equation for OUT is then the logical function implemented in the circuit, using positive logic.

 

Okay, that's what it is using positive logic. But you said you wanted/needed it for negative logic. So see if you can go from here to there.

 

If I used negative logic, I would map the LOW voltage to a logical TRUE (1) and the HI voltage to a logical FALSE (0). The left-most table in the above posting would not change, right, because that is the physical reality of the transistors? However, I would just flip all the 1's and 0's in the other table and the K-map to show that LOW voltage is associated with logical TRUE (1), and HI voltage is associated with logical false (0). Then OUT = ABC +ACD, which is the simplified form of
OUT = ACD + ABC + ABCD = ACD(1 +B) +ABC = ACD(1) +ABC = ABC +ACD

 

If I used negative logic, I would map the LOW voltage to a logical TRUE (1) and the HI voltage to a logical FALSE (0). The left-most table in the above posting would not change, right, because that is the physical reality of the transistors? However, I would just flip all the 1's and 0's in the other table and the K-map to show that LOW voltage is associated with logical TRUE (1), and HI voltage is associated with logical false (0).

Yes. You are definitely making progress.

Then OUT = ABC +ACD, which is the simplified form of
OUT = ACD + ABC + ABCD = ACD(1 +B) +ABC = ACD(1) +ABC = ABC +ACD

Huh?

Again, ask the sanity check questions.

If OUT = ABC + ACD, then that means that if A if FALSE that OUT must be FALSE. Since this is negative logic, this means that if A is HI that OUT must be HI. Is that consistent with the circuit?

After you flip the values in the right-hand table, aren't you left with three terms that are TRUE? What are those three terms (these are minterms, and thus need to include all four variables)?

 

Would the minterms be read from the rows of the truth table as follows?
OUT = A'BC'D' +A'B'C'D +A'B'C'D'

 

That's correct!

Now you can simplify it.

 

From this page http://www.allaboutcircuits.com/textbook/digital/chpt-7/boolean-rules-for-simplification/ I found these identities for Boolean algebra simplification.
1a = a
a +1 = 1
a +a' = 1
a +ab = a
a +a'b = a +b
(a +b)(a +c) = a +bc
OUT = A'BC'D' +A'B'C'D +A'B'C'D' = A'C'(BD' +B'D +B'D') = A'C'(D'(B +B') +B'D) applied a +a' = 1
= A'C'(D'(1) +B'D) = A'C'(D' +B'D) applied a +a'b = a +b
= A'C'(D' +B')
OUT = A'B'C' +A'C'D' , which could also have been found on the K-map

I think my mistake was to not negate the variables using negative logic, right? That's because I had to flip the TRUE (1) and FALSE (0) for negative logic in the table on the right, above. I think I'll just stick to positive logic OUT = C' +A'C +B'D' because it is more intuitive than negative logic.

 

Now you've got it.

Positive logic is definitely more intuitive, but only because that is what we usually use in everyday verbal communication. Negative logic is just as valid and often very useful in both hardware and software. The key is to make a very clear distinction between the physical signal levels and the logic values they represent, which is the purpose served by the two truth tables.

 

....
I think I'll just stick to positive logic OUT = C' +A'C +B'D' because it is more intuitive than negative logic.

C'+A'C can still be simplified.

 

C'+A'C can still be simplified.

Agreed. I was only looking at the negative logic result and missed this.

@J_Rod : This is a very good Boolean identity to get familiar with. It is rather subtle and easy to miss, so if you get good at spotting it then you have a leg up on the competition.

 

Using positive logic, simplifying
OUT = C' +A'C +B'D' applying a +a'b = a +b
OUT = A' +C' +B'D'

 

Yes.

See if you can derive that identity -- it's good practice.

 

See if you can derive that identity -- it's good practice.

Derive a +a'b = a +b? (Using TRUE=1 and FALSE=0, positive logic)
if a=1, 1 +0X = 1 (don't care about b since a is true)
if a=0, 0 +1b = 1b (b must be true for this AND function)
Therefore, for a +a'b = 1, a=1 OR b=1, so we can simplify a +a'b = a +b

 

That's mostly a valid approach -- your last sentence weakens it because while you cover and a=1 or b=1, you don't deal with what it is if both a and b are 0.

For instance, what if I want to show that f(a,b) = 1

I could show that if a=1 that f() = 1 and that if b=1 that that f() = 1. From that I might be tempted to conclude that f(a,b) = a+b, but the problem is that I haven't dealt with f() when both a and b are 0.

Consider the following:

F = A + A'B
F = A(B + B') + A'B
F = AB + AB' + A'B
F = AB + AB + AB' + A'B
F = (AB + AB') + (AB + A'B)
F = A(B + B') + (A + A')B
F = A1 + 1B
F = A + B

 

Is it acceptable to duplicate the AB term in line 4 because the truth value will not change with two of that term?