Hi All,

I have built an edge detector that gives a pulse at every falling edge of an incoming signal. A nor gate compares the incoming signal with an inverted and delayed copy (schematic attached). The detection works (figure 1), but I get a very small pulse also at the rising edge. I checked the input of the nor gate (figure 2 and zoom in in figure 3). It seems that the nor gates sees a double low voltage when the capacitor discharges and the other input is rising. Low voltage level for the nor gate is 1.5V max. Do you guys know what's going on?

Thanks

 

What happens if you remove the diode?

 

The problem appears to be that your input rise-time is significantly slower than the inverter delay and fall-time.
Try adding a small resistance in series with D2 to slow the fall-time on the capacitor.

 

Removing the diode helps. The unwanted spike does not show up anymore. My question now is why? The logic levels should be in the right range.

 

hi V90.
Look at this LTS sim, note the diode current and the time delay between o1 and i2.

E
These delays are in LTS, they will most likely be different in the hardware, but the principle is the same.

 

hi V90.
Look at this LTS sim, note the diode current and the time delay between o1 and i2.

E
These delays are in LTS, they will most likely be different in the hardware, but the principle is the same.

Got it...my idea was to use the diode to get rid of the delay on the rising edge, but it turns out that it is not necessary.

Thanks

 

Removing the diode helps. The unwanted spike does not show up anymore. My question now is why?

As I stated, the input rise-time is so slow that the inverter switches before the NOR gate is inhibited.
So removing the diode (or adding a resistor in series) slows the cap signal enough so you don't get the glitch.
Look carefully at figure 3 of your sim.
See how slow the input signal rise-time is compared to the inverter's fall-time.
Apparently the inverters switching logic level is slightly below the NOR gate's.