Hi,

I'm working through some questions in a textbook on memory systems, and the question asks: "A memory system made of 4 64k by 16-bit memory blocks is connected to a 24-bit address. Make a design for a full address decode circuit, so the memories are arranged at consecutive addresses, starting at 0".

The problem is, as I understand it, that you need 18 address bits (A0-A17) common to each chip, and then you need 2 address lines into a 2-4 line decoder to select the right row (A22-A23).

That leaves A18-A21 unconnected. I emailed my lecturer and he said that this wasn't acceptable as a range of address values would activate the memory, and the unconnected bits must be connected into the decode logic to make sure that unique address values will activate the memory.

Any help is much appreciated.

 

Bits 18 & 19 go to the decoder. Logic to enable the decoder requires bits 20-23 to all be zero. For addresses where the bits 20-23 are non-zero the memory system, does not respond to reads or writes, but there is no harm in doing a refresh if the RAMs are dynamic.

 

To expound on what Papabravo has already pointed out implicitly, you have two problems with your approach.

By using A22-A23 as your chip select bits, you have left a gap in your memory map and the assignment said that the memory was to be contiguous.

By not using the extra bits (whether they be A18-A21 or A20-23), you end up mapping multiple addresses onto the same memory. In this case, each memory address has 16 different addresses that map to it. You want them to be unique, so you have to use ALL of the remaining bits in your decode, but accounting for the unnecessary bits is very easy.

 

To expound on what Papabravo has already pointed out implicitly, you have two problems with your approach.

By using A22-A23 as your chip select bits, you have left a gap in your memory map and the assignment said that the memory was to be contiguous.

By not using the extra bits (whether they be A18-A21 or A20-23), you end up mapping multiple addresses onto the same memory. In this case, each memory address has 16 different addresses that map to it. You want them to be unique, so you have to use ALL of the remaining bits in your decode, but accounting for the unnecessary bits is very easy.

What he said, which sums it up nicely.

 

Fantastic!

Thanks very much for your help guys.

So as I understand it, do I just need to tie all the remaining bits to zero, or actually use them so that the 2-4 line decoder will only work when those 4 spare bits are zero?

Thanks again.

 

Those address lines are OUTPUTS, so do NOT tie them to ground.

You need to decode them. If the value on one of those bits is HI, you do NOT want ANY of your memories to respond at all.

 

Right, okay.

Sorry, I've never come across this before!

Thanks for the help guys.

I'm thinking I could use a four bit NAND to connect the unused bits together, then connect this to the enable of the 2-4 line decoder, or failing that, AND this signal with the outputs from the decoder, so it will only activate memory when those 4 bits are 0?

Would that be a sufficient use?

 

Right, okay.

Sorry, I've never come across this before!

Thanks for the help guys.

I'm thinking I could use a four bit NAND to connect the unused bits together, then connect this to the enable of the 2-4 line decoder, or failing that, AND this signal with the outputs from the decoder, so it will only activate memory when those 4 bits are 0?

Would that be a sufficient use?

The NAND to the enable will work if the enable is active LO.

 

Hi,

I'm working through some questions in a textbook on memory systems, and the question asks: "A memory system made of 4 64k by 16-bit memory blocks is connected to a 24-bit address. Make a design for a full address decode circuit, so the memories are arranged at consecutive addresses, starting at 0".

The problem is, as I understand it, that you need 18 address bits (A0-A17) common to each chip, and then you need 2 address lines into a 2-4 line decoder to select the right row (A22-A23).

That leaves A18-A21 unconnected. I emailed my lecturer and he said that this wasn't acceptable as a range of address values would activate the memory, and the unconnected bits must be connected into the decode logic to make sure that unique address values will activate the memory.

Any help is much appreciated.

Reundant address bits are not uncommon in reality.
If you don't use them, well, they'll do nothing at all.

It is not clear which kind of expertise or trick is sought after here by the teacher.

 

In the days before micro-controllers. I designed a lot of Z80 systems. It was not uncommon then to not do a complete address decoding. As it simplified the decoding. But I guess this is a more academic exercise.

 

The NAND to the enable will work if the enable is active LO.

True! Sorry, I got a bit confused with my logic gates.. Okay, fantastic, thanks very much.

I think it seems to be less common these days to use an excessive address system from what I've read, or to use partial address decoding if there are excessive bits.

I have talked to my lecturer today and he suggested that the question was after the actual decode logic with the addition of some logic gates that will make sure decoder only works when the redundant bits are all zero.

Think I've got it sorted now, thanks very much everyone, very much appreciated!

 

The reason why you might want to decode all of the address bits is so the system can be upgraded later without worrying about potential conflicts. Decoding is rarely done with individual gates any more. FPGAs and chips with internal decoding logic, either input or output, are the new normal.

 

The reason why you might want to decode all of the address bits is so the system can be upgraded later without worrying about potential conflicts. Decoding is rarely done with individual gates any more. FPGAs and chips with internal decoding logic, either input or output, are the new normal.

CPLD? FPGA is very expensive. While a small MAXII CPLD only costs 2 dollar or something like that.