Good afternoon to everybody. First post over here!

I am working on the estimation of junction temperature from top case temperature measurement.
I have seen that manufacturers avoid the characterizing the molding this resistance which is crutial for this purpose.

From now on I will take IPT015N10N5 as a transistor example.
Normally given thermal parameters in datahseets are RthJC and RthJA.
RthJC is obtained by the manufacturer through PN calibration where case is considered as the heat flow path (in this case bottom). See figure below.
On the other hand, RthJA is usually obtained following the JESD51 standart in a test chamber. It is said that the board has to be mounted horizontally as shown in the below figure.
However, in the IPT015N10N5 datasheet it is said that for this characterization, it has been mounted vertically. 
I am doing some experiments both horizontally and vertically with minimum footprint and 6cm2 of copper area to try to replicate results. I have made a hole at the footprint to measure drain temperature and placed K thermocouples and IIR FLIR Camera.



Does anybody know the reason why is it mounted this way?
Do they really mount the test chamber or do they simulate it through CFG in softwares as ANSYS?
If they really use the chamber. How about the wires power dissipation? Do they take them into account?
I have not seen previous work that has this same aim. Does anybody have a reference paper? (This is the closer paper I have found but they use a specific software that is no longer availabe: Vishay)
Thank you in advance,
José Miguel.
I am working on the estimation of junction temperature from top case temperature measurement.
I have seen that manufacturers avoid the characterizing the molding this resistance which is crutial for this purpose.

From now on I will take IPT015N10N5 as a transistor example.
Normally given thermal parameters in datahseets are RthJC and RthJA.
RthJC is obtained by the manufacturer through PN calibration where case is considered as the heat flow path (in this case bottom). See figure below.

On the other hand, RthJA is usually obtained following the JESD51 standart in a test chamber. It is said that the board has to be mounted horizontally as shown in the below figure.


I am doing some experiments both horizontally and vertically with minimum footprint and 6cm2 of copper area to try to replicate results. I have made a hole at the footprint to measure drain temperature and placed K thermocouples and IIR FLIR Camera.



Does anybody know the reason why is it mounted this way?
Do they really mount the test chamber or do they simulate it through CFG in softwares as ANSYS?
If they really use the chamber. How about the wires power dissipation? Do they take them into account?
I have not seen previous work that has this same aim. Does anybody have a reference paper? (This is the closer paper I have found but they use a specific software that is no longer availabe: Vishay)
Thank you in advance,
José Miguel.