Eprom 27256 need help

Discussion in 'General Electronics Chat' started by vead, Sep 17, 2016.

  1. vead

    Thread Starter Well-Known Member

    Nov 24, 2011
    I am looking information for 27256 ic.
    A0-A14 are the address pins
    D0-to D7are data pins
    CE chip enable used for rom selection
    OE out enable pin
    I was reading datasheet. I have confusen what is meaning of address are stable?. I am trying to explain my understanding using example. Correct me if I am wrong.
    Code (Text):
    1. Address 15 bit         data 8 bit                      
    2. Address 0:                  xxxxxxxx
    3. Address 1:                  xxxxxxxx
    4. Address 2:                  xxxxxxxx
    5. .
    6. .
    7. .
    8. Address 14:                xxxxxxxx  
    xxxxxxxx means anything ie. 01001010, 010 01111..etc
  2. Robin Mitchell

    Distinguished Member

    Oct 25, 2009
    When you set up your control signals (address, CE etc) you need to wait for a while before the output data bus is stable. As you change inputs the data bus will also be changing and that change takes time so in order to ensure that your data is correct for your chosen address you need to wait a while (it will be in the 100's of nano seconds normally).
  3. dl324

    AAC Fanatic!

    Mar 30, 2015
    If you quote the text in question, it will be easier to explain from the context.
    I assume you mean why addresses must be stable for tACC before data is valid. It's the delay in propagating the data to the outputs.

    Depending on what is connected to the EPROM you're trying to read, you may be able to leave CE# and OE# low, change the address, wait tACC, and read data; for each address you want to read.
    absf likes this.