Im making this cct for fun. Ive seen it in a video on youtube, with different IC's. So I decided to adapt the cct to what IC's I already have.
And it is working perfectly, both in simulator and in reality (on breadboard). But while building it, testing it, and playing with it, I noticed a problem.
If button S53, the one with C4 in parallel to it, is pressed, it will bounce a bit, and the CLK on pin 3 will activate -multiple- times. Most of the time, the contact is as it should, only once and the CLK will be activated normally. But in random times, the button will bounce, depends the way Im pressing the button I guess. The cct behave like this: doesn't matter how many times any other button will bounce, it will still create the logic flow, correctly, even if Im purposely press, for testing reasons. But this last CLK button, S53, is tricky in the logic chain. If pressed once, it will activate the Unlocked LED, and the AND gate will set to LOW, the first 3 CLK's. But if pressed once more, the second time, it will toggle the LED off, but also the AND gate, and in turn, it will reset the entire logic flow to it's start.
My question to you is this:
- How to make S53 be pressed only once, and on other presses, doesnt matter if bounced or intentionally by my finger, to not clock anything anymore. The only real reset will be S54. So far, I can reset from 2 buttons, S53 and S54. But S53 should not reset the cct, only S54.
This is more as a fun challenge.
My immediate solution is to use another FF (Flip-Flop) only for this S53 button. But... Im afraid I might complicate things way too much.
Im very curious what you will come with.
Thank you.
(click the image to enlarge and zoom in)

 

I'm confused about the purpose of R33 - R36 being connected to ground with the switches across them - unless the diagram is drawn wrongly. Normally I would have expected the resistors to be pullups to 5v as in the original circuit. Both 4013 and 7474 FF are rising-edge triggered, but in your version the rising edge is actually a movement from ground to floating + a 10k pulldown. If this is truely the case then I'm not surprised clocking is unreliable!

 

I'm confused about the purpose of R33 - R36 being connected to ground with the switches across them - unless the diagram is drawn wrongly. Normally I would have expected the resistors to be pullups to 5v as in the original circuit. Both 4013 and 7474 FF are rising-edge triggered, but in your version the rising edge is actually a movement from ground to floating + a 10k pulldown. If this is truely the case then I'm not surprised clocking is unreliable!

- Thanks. I see your point now. It might be wrong the circuit I built, because I adapted it to my IC's that I have, and I am into learning the logic IC's (in general). Although, this cct presented here, is still working fine both in the simulator and in reality, exactly as you describe it "the rising edge is actually a movement from ground to floating + a 10k pulldown". Excelent observation btw. I completely overlook it.
- Here is the modified circuit, with all the CLK resistors pulled up, more correctly this way indeed.
The functionality of the cct still remains the same. Which is very good, Im actually amazed it worked with the floating CLK pins, haha.
- The problem we are facing here is a --LOGIC-- problem (not IC Logic, but Human Logic) on the 4th CLK pin.
- That S4 switch/button on the 4th CLK is doing what is supposed to do. Im not criticizing its functionality. It is good. But the cct intention should be, from a human perspective, to have only 1-one reset button on SR, and not 2 resets on S4 and SR. You get my point now? So that S4 is doing what it supposed to do, but I dont want it like that, I want it clock only once and disengage after 1 clock, and if Im pressing S4 again, noting will clock because is disengaged. Very interesting problem, dont you think?
- All the other CLK's, the first 3 of them, are automatically disengaged by the AND gate when the S4 is pressed for the first time ! The FF's themselves are being put into reset, thats why the AND gate is there. I did build the cct without the AND gate and the behaviour is weird, not as clean as it (mostly) is now.
- I renamed manually, the automatic renaming of the S's, and all the values are changed a bit from the original post. Now should be better.

And if you were wondering, this is how it looked in the video of the guy on youtube:

 

And, I find a solution ! Yay... but is a bit more complicated than I wanted. It is working fine now... but too much stuff. Hmmm.
....
I find 2 solutions now. One with the 4081 AND Gate IC and another using only discrete components. The second one was... HARD, but worth it. Aaaah.
Still, a lot of circuitry for a single bastard button.... But it is exactly as I want it now. Aaaah.

 

I find an even simpler solution and also I find a terrible mistake I made. I realized way to late, that all those S (Set) pins are inputs, and as some have said to me in the past conversations, every input for any logic IC should be put to the + or - rail, to avoid spurious and erroneous output behaviour. And is exactly what I just got. But... a bit too late. So the very big mistake I did was to Not convert properly the original cct into my ICs that I have ! It remains as a lesson for me.
Here is the new updated cct, with better performance than I was having it before. Im actually very proud I find the problems and make it better.

 

I have avoided using 7400 series TTL, and only used 4000 series CMOS, first because it uses so much less power, and second because the logic manuals were much better. Also, many TTL devices had low-true inputs instead of hi=true inputs. At least that is what I found in 1972. And the fan out with CMOS is far more forgiving.
And now you have discovered that it was a floating input that caused the problem?? That certainly is a reasonable solution.

 

There is still an error on your last schematic - the reset pins have no pull-up to 5v.

Also, C9 isn't needed because even if s100 bounced its still only clocking in the 1 from the Q on FF #'3, unlike earlier when setting Q #4 high reset FF #1-#3 and therefore the bounce could propagate the subsequent 0 on Q#3.

 

There is still an error on your last schematic - the reset pins have no pull-up to 5v.
Also, C9 isn't needed because even if s100 bounced its still only clocking in the 1 from the Q on FF #'3, unlike earlier when setting Q #4 high reset FF #1-#3 and therefore the bounce could propagate the subsequent 0 on Q#3.

Indeed and very true. Ive notice it as well. But is good you confirm it to me.
Here is the updated version:

I believe I start to understand why the orig cct was using a NAND gate for the last #4 FF. It was that the rest of the input code, not to be visible if leds are added to each Q output of each FF in the series. To automatically switch them off. Thats why the trouble. Very interesting cct !

 

Even with this last circuit there still exists a way to find the numbers in the combination with only access to the keypad connections. That is because all of the unused numbers are tied in parallel. So probing the switches with one button pressed will reveal which buttons will pull down the unused inputs. So checking voltages can reveal that either the first button is a valid number, if none of the other numbers change, or an unused number it many of the numbers change, which then the used numbers are revealed with the same test.
Thus this combination lock is not so very secure from a slightly competent hacker.

 

Even with this last circuit there still exists a way to find the numbers in the combination with only access to the keypad connections. That is because all of the unused numbers are tied in parallel. So probing the switches with one button pressed will reveal which buttons will pull down the unused inputs. So checking voltages can reveal that either the first button is a valid number, if none of the other numbers change, or an unused number it many of the numbers change, which then the used numbers are revealed with the same test.
Thus this combination lock is not so very secure from a slightly competent hacker.

Haha, most probably. It is a fun project and a reason to learn something new about FF and logic ccts.

 

Haha, most probably. It is a fun project and a reason to learn something new about FF and logic ccts.

For learning about IC logic, consider that the 7474 FF device is almost 50 years old, and has low=true inputs for set and reset, mixed with leading edge triggers for clock and data. In addition, it consumes more power than CMOS logic, and demands a rather closely controlled supply voltage. So as a choice for design it is not very good. CMOS logic is useful with supply voltages running from 3.3 volts up to 15 volts for most devices, and it consumes far less power, as well. So a CD4013 will work well in the circuit with only revisions in input levels.

 

4013 is the chip used in the original cct. But I dont have that chip. I probably get some in the future. But for the moment I am using what I have. This was a project to adapt an learn new things about logic ICs. And it was very educative so far, I didnt expect it to be this hard. I complicated things a bit but for the purpose of learning the thing.
Ok... I have 2 interesting Questions for anyone here looking to my posts.
-Question1- What is the role of that 4011 NAND gate in the original cct ?
I have 3 Theories about its role.
- T1: The role of the NAND gate is to automatic deactivate S1 to S8 AFTER LED1 is ON, by setting HIGH the first 3 Gates Reset pins, resetting them, until S9 or S10 is pressed, that in turn will reset only the 4th gate.
- T2: If it is indeed a gate used to reset the first 3 FF's, why in the hell didn't do it like I did it? Linking all 4 Reset pins together. I am still absolutly perplexed why he used it there. It still has no sense to me. The only logical sense is if it was having some LEDs there, that he didnt wanted to keep them open when the last digit in the opening code was activated. For curious eyes, not to see which leds/buttons were activated. But it is not having any LEDs in the cct either. It is a true mystery that NAND gate there.
- T3: The designer didnt know anything about logic ICs and he slap it there, just because, no reason whatsoever. Just to make a Bigger cct, for appearances that it is 'complicated' and fancy. He might be an idiot.

- - -
-Question2- Now the fun part! Hehehe. I already solved this problem. I worked on it probably 1 day and I figure out a solution. It is working fine in simulator, but I didn't test it on the breadboard. But I will very soon, just to be sure. If you like to play logic games, like I do, give it a try. I will post the cct I made, but after awhile. Not right now. I will give you time to think.
So... the cct we are using is from post #8 and the problem is like this:
- How would you add a LED for each Switch in the cct? To light when the button is pressed, but not all LEDs at once! Only when you press a certain button, its corresponding LED, let's say it's "parallel" LED, will lit up, telling you THAT button is in pressed state.
I will give you a hint. There are 2 sets of switches. 1 set are all linked between them and to the Reset pins, and 1 set are the ones for the Clocks. You will have to adapt to each set.
Again, I solved the problem and it is a very cool one. Haha. Happy designing !
Im very curious if you will come with the same or similar solution as mine, or completely different approach. Or nothing at all. Haha. Good luck. Let's see who will be the winner ! Haha.

 

The 4081 is there to pull UP through the resistor, because the 7474 set and reset are LOW=True devices. Clock and Data are rising edge/hi=true inputs. That is another reason I never used the device.

 

Here is the progress so far. Only 4/6 button modules are made so far. In the final cct I linked 6 Reset pins toghether and 4 buttons for clock pins. In total 10 btns. I tested what I have here and working just fine. But is hard work and slow. Slowly but surely.
All the components are scrapped and repurposed. Those leds are VERY old, 80's or 90's and quite dim to today standards. But bright enough for this application.

 

All 6 Reset Button modules are made. Quite an effort and patience.

 

Here is the Clock Button:
Only 1 now, and I have to make 4 of them. Its much simpler than the Reset buttons.

+ a little test

 

WOW! That is a construction technique I am not familiar with. Usually for a electronic lock system the buttons and a minimum amount of circuitry are in a hardened package that is accessible while the decode and unlock control are located in a secure area.
A while ago I came up with a scheme, actually just the detailed specification, for a combination door lock that would be able to allow different groups access to a building only when they were supposed to be using it.
Now I have been seeking a suitable low cost PLC to run the code, and that has been the challenge.

 

I am not a Lock designer. I am making these for fun. Nothing practical in mind. And also, most important, its my FIRST (electronic) lock I ever made. In a sense, this is a prototype. This is not the entire cct. I have to add other circuitry, and most probably on the back of the button panel. Wish me luck. Im glad you like it so far. I can tell you, this is hard to make ! I was actually thinking on a way to prevent hacking, as you pointed out some posts ago. I have something in mind but very unsure if I will actually implement it, because it will add some thickness to the entire cct that will already be more thick than usual smd + mcu as everything is made today. This one will be big and I know it. But functional, and is good enough for me. Ha.

 

All the buttons + leds [modules] are done. What a day ! Phiew.

 

And, for completion, here is the end of the project:
youtu.be/tEnsiDDIbU8 ____43min
youtu.be/lov93I3KpZE ____13min - I suggest to start with this one because is shorter time.
For anyone that likes my progress.