I have this scheme:

And here is my test code:

clock_proc : process begin -- sinchrosignal ą valdantis procesas
x1 <= '0';
wait for 8 ns ;
x1 <= '1';
wait for 8 ns ;
end process ;

reset_proc : process begin -- nustatymo i 0 signal ą valdantis procesas
reset <= '0';
wait for 2 ns ;
reset <= '1';
wait ;
end process ;                            

test_proc : process begin -- trigerio signalus valdantis procesas
x2 <= '0'; x3 <= '0'; x4 <= '1'; -- saugo
wait for 5 ns ;
x2 <= '1'; x3 <= '1'; x4 <= '0'; -- iraso 0
wait for 5 ns ;
x2 <= '0'; x3 <= '0'; x4 <= '1'; -- saugo
wait for 5 ns ;
x2 <= '1'; x3 <= '1'; x4 <= '1'; -- iraso 1
wait for 5 ns ;
x2 <= '0'; x3 <= '0'; x4 <= '1'; -- saugo
wait for 5 ns ;   
end process;

It should reset Q to 0 at the beginning, then hold, then reset it to 0, then hold, then set it to 1 and then hold. But what I get is this:

As you can see, at the beginning when Q should be reset to 0, it is set to 1 and then stays at 1 till the end. J and K are okay, so I guess something is wrong with my scheme, but I can't find the issue.

It would be great if someone could check out it and maybe spot the mistake.

 

Have you implemented this layout using a set of Boolean equations? If so, I'd recommend going through each data path and find out if your implementation matches your equations.

What are x1-x4 supposed to be/do?

 

Have you implemented this layout using a set of Boolean equations? If so, I'd recommend going through each data path and find out if your implementation matches your equations.

What are x1-x4 supposed to be/do?

I used the same boolean equations while doing the static JK trigger, and it works fine. Even master-slave implementation is done great, so I guess equations are OK.
I add them here, not a lot of computations.


And x1-x4 are the inputs. I assign values to them in my test code.