Note that you cannot conduct a real life experiment in order to determine whether the output would be truly random, just in case you want to try it.

Any differences in propagation delay between the J and K inputs, even picoseconds, would result in consistent results.
Differences from one chip to another can give consistently different results.

The take away here is that you must study and comply with setup and hold times as specified in the manufacturer's datasheet. In other words, there is a minimum setup time (tsu) for J and K to be stable before the clock edge arises and a minimum hold time (th) that J and K must remain stable following the clock edge.

 

However, the fact that the problem you are given has the J and K input changing away from the clock edges calls this assumption into question since they are clearly asynchronous. Therefore you can approach it a couple of ways. First, you can say that the input state is unknown and see if it makes a difference. If it doesn't, then life is good. If it does make a difference, then the output is unknown after the transition. Another approach would be to state your assumption regarding the find details of the signal changes near the clock edges.

Thank you for replying. I also thought the same of assuming the values of inputs. I assumed three scenarios:
1). The output is indeterminate since the inputs are not static at the edge. So the answer is "Indeterminate Output"
2). The signal which we consider for input is the one at the start of the edge triggering. So, I created the waveform for both negative and positive triggering based on this assumption. So, for positive edge-triggering based on this assumption, we get:



3). The signal for input would be the one at the end of edge triggering. Similarly, the waveforms will be different compared to the 2nd scenario. So, for Positive edge triggered based on this assumption:



P.S1. I know in real-life these phenomenons will not occur or either of them could occur as the real inputs will have at least some delay and setup and hold times.


Thank you everyone!

 

An interesting question this,

so there are two parts ot this

The circuit is digital , as some ones handle says there are 10 types of people, those the get binary and those that don't,

So although, we draw clocks and signals changing together , in reality , that is "impossible"
the timings are such that either the input is going to be a 1 or a 0 at the point the clock crosses its threshold.

The usual convention is that is a signal on the input is a value before the clock and different after the clock, then its the value before the clock we use.


If you want extra marks,
look up metastability,
its what can occasionally happen to an output where the input is just at the right level at the clock threshold time
its a real pain when clock speeds get faster and inputs are asyncronous.

 

There is yet another answer.

1) If both J and K inputs are changing during the clock transition then the outcome of Q is indeterminate.

2) If J is changing, K = 0, and Qn = 1, then the outcome is Q(n+1) = 1 after the clock transition.

3) If K is changing, J = 0, and Qn = 0, then the outcome is Q(n+1) = 0 after the clock transition.

This does not apply in the situation as shown in your diagrams.

 

After much research, I found this in a book on Digital Systems. It says to consider the value before triggering so I guess I will have to go with my 1st and 2nd scenarios for homework.

The book is Digital Systems by Ronald J. Tocci, Neal S. Widmer and Gregory L. Moss.

Thank you @andrewmm, you also mentioned the same thing in one of your previous answers.

 

Define "just prior".

Let us look at some real numbers. The datasheet for negative edge triggered J-K flip-flop SN74LS112 and SN74HC112 both show tsu = 20ns minimum and th = 0ns.

Hence if we can define "just prior" to mean greater than -20ns then we can use the prior values of J and K inputs.

If the J and K inputs are changing at any time from -20ns to 0ns then all bets are off.

 

Define "just prior".

Let us look at some real numbers. The datasheet for negative edge triggered J-K flip-flop SN74LS112 and SN74HC112 both show tsu = 20ns minimum and th = 0ns.

Hence if we can define "just prior" to mean greater than -20ns then we can use the prior values of J and K inputs.

If the J and K inputs are changing at any time from -20ns to 0ns then all bets are off.

Here just prior means the value of Input right at the start of edge triggering. But you'll also have to understand that this is not a real J-K flip-flop, it is a just a homework/theoretical question, so of course, the real one will have at least some aperture time.