The thing is that I'm making a BLDC and I'm using a half-bridge configuration where the driver outputs were initially connected with a low value resistor to the MOS Gate of the half-drive. With Spice it seems that the resistor has to be approximately 50 ohms so that it does not produce a current peak at the driver output higher than shown in the datasheet capture (output current values Io+, Io-) and can damage it, but I do not know if this resistor is really necessary or not, because I do not see if the driver really has that protection block that would allow me to remove the resistor and connect directly the driver output to the MOS gates. That is to say, I don't know if the maximum admissible current in the driver output takes those values of the datasheet and really the driver IC would burn if we exceed the value of this current or if there is a protection block that would prevent that from happening and, therefore, I can get rid of the resistor. Thanks!

 

I thought the purpose of the resistor was to avoid ringing due to trace inductance resonating with the inherent capacitance of the gate electrode. The gate resistor does not have much effect on the drain current. That is a function of the difference between Vgs(th) and Vg. The higher the gate voltage, the lower the Rds(on), and the larger the drain current. I'm not at all sure what you mean by a protection block. There are no DC currents to speak of that will cause a problem. what might cause a problem is spending an inordinate amount of time with the MOSFET in the linear region and the resultant heat buildup.

 

I thought the purpose of the resistor was to avoid ringing due to trace inductance resonating with the inherent capacitance of the gate electrode. The gate resistor does not have much effect on the drain current. That is a function of the difference between Vgs(th) and Vg. The higher the gate voltage, the lower the Rds(on), and the larger the drain current. I'm not at all sure what you mean by a protection block. There are no DC currents to speak of that will cause a problem. what might cause a problem is spending an inordinate amount of time with the MOSFET in the linear region and the resultant heat buildup.

What I am referring to the importance of the gate resistor for the driver is that I have simulated this circuit, parametrizing the gate resistor in several values and I obtain the simulation where a current peak is appreciated in the Gate of the MOS and, therefore, in the output of the driver, of the order of 100-330 mA depending on the value of Rgate. But then I have some data from the driver datasheet (Io+, Io-) that indicate a minimum current peak of 120 mA and a maximum of 200 mA, for example. My question is, if there is no protection element in the driver (which I do not see and I would like to know if someone can tell me), I understand that the optimum resistance would be between 50 and 60 Ohms to be close to the 120 mA minimum current at the driver output according to datasheet, but to what extent is this resistance necessary? The driver has a protection for that peak current that makes it possible to get rid of this gate resistor? Thank you.

 

You are not seeing the forest for the trees. Please take another look at the datasheet and tell me ALL of the conditions that are mentioned. Not just the peak current but also any conditions on voltage and time.

Then notice what you are asking the MOSFET to do. The Miller capacitance in conjunction with the gate resistor is creating the plateau in the gate current which delays the turn on. This is precisely what the gate driver is designed to avoid. Any protection device inside the gate driver would do more of the same thing. Notice also that in all cases the current decays within a very short time frame, because this is NOT a DC current.

Looking at the block diagram of the chip(Functional Block Diagram, p.4), the only protection is the rds(on) of the MOSFETS used internally to construct the output stages which won't amount to much. Interestingly in Figures 22-29 there are curves which show the temperature of (various MOSFETS ??) as a function of frequency with Gate resistance and VDD as parameters. This suggest that some gate resistance is expected but it seems to be limited to values from 10 Ω to 33 Ω. This is a bit less than your simulation would indicate and confirms that when trying to switch at high frequency there are considerable power losses to deal with. I think this is the bigger problem as opposed to the AC gate current. What do you think?

Notice also that you are using an ideal voltage source with no parasitic elements for driving the gate. This is going to produce results that are unobtainable in practice. You need a better model of the gate driver to make a truer picture of reality. Try driving it with a current source instead, observing the pulse width limitation mentioned in the datasheet. Don't forget trace inductance.

 

Note that those short-circuit current limits are for a 10µs pulse.
Your currents are for less that a microsecond, so should not be a problem.

 

You are not seeing the forest for the trees. Please take another look at the datasheet and tell me ALL of the conditions that are mentioned. Not just the peak current but also any conditions on voltage and time.

Then notice what you are asking the MOSFET to do. The Miller capacitance in conjunction with the gate resistor is creating the plateau in the gate current which delays the turn on. This is precisely what the gate driver is designed to avoid. Any protection device inside the gate driver would do more of the same thing. Notice also that in all cases the current decays within a very short time frame, because this is NOT a DC current.

Looking at the block diagram of the chip(Functional Block Diagram, p.4), the only protection is the rds(on) of the MOSFETS used internally to construct the output stages which won't amount to much. Interestingly in Figures 22-29 there are curves which show the temperature of (various MOSFETS ??) as a function of frequency with Gate resistance and VDD as parameters. This suggest that some gate resistance is expected but it seems to be limited to values from 10 Ω to 33 Ω. This is a bit less than your simulation would indicate and confirms that when trying to switch at high frequency there are considerable power losses to deal with. I think this is the bigger problem as opposed to the AC gate current. What do you think?

Notice also that you are using an ideal voltage source with no parasitic elements for driving the gate. This is going to produce results that are unobtainable in practice. You need a better model of the gate driver to make a truer picture of reality. Try driving it with a current source instead, observing the pulse width limitation mentioned in the datasheet. Don't forget trace inductance.

Right, thanks for the information. It has been very helpful to see where I may have the problem and I think I was thinking about it wrong, I will rethink it with the driver model I use and see what I get.

 

Is your SPICE time-interval set short enough. Those graphs seem rather too straight and angular for real waveforms!

 

Note that those short-circuit current limits are for a 10µs pulse.
Your currents are for less that a microsecond, so should not be a problem.

Exactly what I was trying to get the TS to notice. We often have a tendency to look at the "headline" number in a datasheet without looking at the complete set of test conditions. It is easy to overlook the time scale of the TS's simulation which is less than a microsecond. Switching a MOSFET gate that fast is generally speaking difficult with less than ideal components.