Hello,

I am currently working on improving and correcting the hardware design of two of my company's products. One is a small board measuring 55.499 x 31.369 mm, based on an ESP32-PICO D4() and an STM32G070, both operating at 3.3V. It includes a pair of 12V output relays. The previous design follows the following format:

Layer 1 (TOP): Components, signals, and a GND polygon all over the layer.
Layer 2 (Signal 1): Some signal traces and the rest covered by a 3.3V plane.
Layer 3 (Signal 2): Some signal traces and the rest covered by a GND plane.
Layer 4 (BOTTOM): Few signal traces and the rest covered by a GND plane.

The other board is slightly larger, measuring 148.717 mm x 76.708 mm, with an ESP32 WROOM module, STM32G070, a 4G module, 4 output relays, and Wiegand and RS-485 output communication. It follows the following configuration:

Layer 1 (TOP): Components, signals, and a GND polygon all over the layer.
Layer 2 (Signal 1): Some signal traces and the rest covered by a 3.3V plane.
Layer 3 (Signal 2): Some signal traces and the rest covered by a GND plane.
Layer 4 (BOTTOM): Few signal traces and the rest covered by a 3.3V plane.
Both boards have serial output and SWI (STM32 only) for debugging and code loading.

The designs come with many errors and issues, which leads me to question whether the choice of format is the most appropriate. Therefore, I would appreciate it if a more experienced hardware designer could provide their opinion.

Thank you.

 

you covered everything but the software you use and errors/issues you encountered.... how in the world can anyone try to help you?

 

The choice of format normally only becomes important,(even if one format stack might be better for handling critical sections) where signals and bypass routes are critical. We need some sort of example on these boards where that is true and caused a problem.

 

when signals are critical, things like shielding, matched length etc become important. shielding could be improved if layers are alternated so that GND or power plane layers separate signal layers. instead of signal>signal>power>power, you may want to use signal>power>signal>power or signals>power>power>signal... or... if the two signal layers need to be adjacent, run the traces perpendicular to each other. so if traces on one layer run east-west, then next layer should have them oriented north-south. for small boards length of traces is of course limited which reduces any potential for interference or crosstalk. since problems are present (whatever they may be), it is more likely things are related to poor circuit design, missing bypass capacitors etc. if this is DIY assembled, i would check how clean the board is, any contaminant including flux, solder blobs etc would need to be removed.... check for cold solder joints. if there are connectors and terminal blocks they would need proper mechanical strain relief. this means they need to be seated flush against the board before soldering, should have correctly sized pads and traces connecting to them. without that it is likely that during handling board can get damaged, and one you have cracked trace it can be nightmare to find. i mean one go ad nauseum guessing what can be wrong. those are just some off the cuff tips. to really help you with your board issues, we need to see your boards and what the problem is.