Dont Care terms: Question Digital circuits

Thread Starter


Joined Sep 20, 2017
I am having trouble understanding the highlighted portion, see attached.

I understand that in a BCD, range from 0 to 9, so in a truth table 10 to 15 are "Dont cares." But how in the truth table attached are they "Dont care?"

Thanks in advance.



Joined Jan 29, 2010
hi eng,
The don't cares in your example are specific to that problem only.
It means the Input combinations will not include those don't cares.

Your BCD question is not related to this question, you are correct if you were explaining the combinations for a BCD value from 0 to 9.



Joined Feb 24, 2006
In practical terms it means you can assign either a 0 or 1 to any don't care. This may make your implementation of the Boolean function easier, that is using fewer gates.


Joined Aug 1, 2013
But how in the truth table attached are they "Dont care?"
IF N2 is a bunch of combinatorial logic (gates, registers, etc.) driven by three input bits A, B, C, and producing one output bit F,
AND IF F is not a tri-state output that can assume a state that is neither 0 nor 1,
THEN there will be a 0 or 1 value of F for all 8 possible input states.

However, depending on the application, all 8 output values might not be useful, important, necessary, valid, etc. Any output state that can be totally ignored forever no matter what is called a don't care state. The actual values F has for the two disallowed conditions will vary depending on the exact circuit inside N2, but no one cares so those values are not a part of the specification for the N2 circuit.

Continuing, if there is an input bit that has no affect on any of the output states, then that also is called a don't care, only this time it is a don't care input. This can come up when decoding a block of addresses or dealing with a data pattern that has more information than needed for a specific task. For example, a relatively complex counter chip is the 74160 synchronous counter. It has a clock input, three control inputs, and an *asynchronous* reset. This means that when the reset input is active, all of the other inputs are 'don't cares' because they can have no effect on the outputs.