in the truth table of SR latch when S=R=1 o/p of latch is Q=~Q=0 which is invalid state.
While deriving the characteristic eqn for next state of SR latch, we use the k-map so when S=R=1 ; next state o/p is marked as X (Don't Care). we group four adjacent ones in k-map & two adjacent ones finally the o/p of SR Latch is Q(n+1) = S + Q(~R).

My question is since S=R=1 o/p of both NOR gate are 0 ( Q=0 & ~Q=0).
instead of marking zero in K- Map Q are Marked as X??? why so? as X (Dont Care) can be 0 or 1.

 

If S=R=1, the outputs will be in an indeterminate or undefined state.
It's not so much a "Don't Care" as a "Don't Know" what they are, as it's not defined. It is not a logical state to instruct the IC to perform, as it cannot be both SET and RESET at the same time.

If you tried this on an actual part, you'd likely find that the Q and Q\ outputs had a good deal of noise on them instead of a steady logic state.

A NOR gate is different from a SR latch.