Domains active during Microcontroller Sleep mode?

Thread Starter

Abhinavrajan

Joined Aug 7, 2016
83
Hi all,

Can some one tell me what are the domains active during the MCU sleep mode?

I tired google. but unable to find the exact answer.

Thanks.
 

danadak

Joined Mar 10, 2018
4,057
You have to look at actual specific part data sheet and tech manual to
find out what is being placed into sleep and what is kept alive or in reduced
power. One family (vendor) to another this is not the same. And there are
usually a table of modes available in processors to tailor HW vs power
capabilities. One example -

upload_2018-12-3_6-5-49.png


http://www.cypress.com/file/121271/download


Regards, Dana.
 

Thread Starter

Abhinavrajan

Joined Aug 7, 2016
83
You have to look at actual specific part data sheet and tech manual to
find out what is being placed into sleep and what is kept alive or in reduced
power. One family (vendor) to another this is not the same. And there are
usually a table of modes available in processors to tailor HW vs power
capabilities. One example -

View attachment 164922


http://www.cypress.com/file/121271/download


Regards, Dana.
Thanks a lot Dana. But this was a question from a competitive exam which asked the question in general without any other inputs. Like mention the active domains of MCU in sleep mode. I tried many websites. But failed. Thank you very much for the response. However, is there a general answer to that general question?
 

jpanhalt

Joined Jan 18, 2008
11,087
I am only familiar with PIC's. Here is a general link to the 8-bit devices: http://ww1.microchip.com/downloads/en/devicedoc/33023a.pdf

Generally, interrupts not dependent on the system clock and resets will work if enabled. As for the interrupts on 8-bit devices, TMR0 is not active (depends on system clock), but TMR1 ( a "peripheral") is.

Here's the list for a enhanced mid-range device:
Source = datasheet
1. External Reset input on MCLR pin, if enabled
2. BOR Reset, if enabled
3. POR Reset
4. Watchdog Timer, if enabled
5. Any external interrupt
6. Interrupts by peripherals capable of running
during Sleep (see individual peripheral for more
information)
The first three events will cause a device Reset. The
last three events are considered a continuation of
program execution.
 

danadak

Joined Mar 10, 2018
4,057
I think exam question way too broad, as all processors do not share
the same domains.

That being said all processors have a clock domain, interrupt domain,
memory domain (several).....


Regards, Dana.
 

jpanhalt

Joined Jan 18, 2008
11,087
Perhaps something general like,"Anything that is not disabled or dependent on something that is disabled will work during sleep." Then to show that you are not being "smart," I would add a specific example from the MCU's with which you are familiar.
 
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