I have to change this circuit so it will work with all NAND gates. My first step is labeling all the gates. Can somebody tell me if I have labeled all these right.
Thanks

 

I see signals labeled, but no gates. Gates normally get designators like U1A, or Z1A. The pins are numbered to correspond with the actual device. The devices shown, by their MIL-STD806C outlines are inverters, AND gates, and OR gates.

Your B example has three outputs. It is conventional to make up a truth table for each one. It would have the state of the A and B inputs followed by the state of that particular output.

Take the lower AND gate in example A. Assuming you're using 74LSxx family logic, it would probably be a 74LS08. Being the second one on the schematic, it would probably be U2B, where the inverter (a 74LS04) would be U1. Then U2B's pins would be 4 and 5 for the inputs and 6 for the output pin. With the logic family identified, we then know what signal levels to expect. We can look up the device's data sheet if there is any question about signal tining or weather the function goes on a HIGH or a LOW. And we can discuss the state of U2B pin 6 relative to pin 4 and pin 5. It lets everybody read the map the same way.

 

The outputs which you have put on are correct.

 

I have to change this circuit so it will work with all NAND gates. My first step is labeling all the gates. Can somebody tell me if I have labeled all these right.
Thanks

Can I point out in (b), the lower AND gate with inputs DBD' is a superfluous gate since DD' will always equal 0. In other words no matter what input combination DBD' is the output will always be 0.

Therefore you can simplify both your gate-layout and expression.

Dave