# Digital input and find output questions

#### Benengineer

Joined Feb 6, 2016
133
Your description is too difficult to follow. We use timing diagrams to convey that type of information.

Show the waveforms for all flip flops to show how you came up with Y.
I think the picture is already showing every D flip flops. I don't know what else I should show here. I showed every cycle how to transition.

#### dl324

Joined Mar 30, 2015
15,511
I think the picture is already showing every D flip flops. I don't know what else I should show here. I showed every cycle how to transition.
The picture doesn't show the outputs of any of the flip flops.

#### Benengineer

Joined Feb 6, 2016
133
The picture doesn't show the outputs of any of the flip flops.
Sorry, I don't know how to answer your questions. I don't know what you really want.

#### Benengineer

Joined Feb 6, 2016
133
Do you think it is something wrong? Please let me know.

#### dl324

Joined Mar 30, 2015
15,511
Sorry, I don't know how to answer your questions. I don't know what you really want.
A timing diagram:

You can see from the timing diagram that when Preset is de-asserted, the flip flops (CDAB) are at the desired initial state of 1000 (LOW is near the bottom of the label letters and HIGH is near the top).

#### Benengineer

Joined Feb 6, 2016
133
A timing diagram:
View attachment 152566
View attachment 152567
You can see from the timing diagram that when Preset is de-asserted, the flip flops (CDAB) are at the desired initial state of 1000 (LOW is near the bottom of the label letters and HIGH is near the top).[/Q
Thanks.
The question asked us to show Y at continuous state.

#### dl324

Joined Mar 30, 2015
15,511
The question asked us to show Y at continuous state.

#### WBahn

Joined Mar 31, 2012
28,185
A picture is worth a thousand words.

Look at the clock edges that your solution transitions on.
View attachment 152562
How can the two Y pulses transition on different edges of clk?
That was my immediate thought, too. But look at the diagram. The Y signal is not the output of a FF, it is the output of a logic gate in which one input is from a positive-edge triggered FF and the other is from a negative-edge triggered FF.

#### WBahn

Joined Mar 31, 2012
28,185
Please see this pictures I did. It may be clear.
View attachment 152564
That's a different result for Y.

Please don't describe what is happening in words (at least not as the only description).

I think the picture is already showing every D flip flops. I don't know what else I should show here. I showed every cycle how to transition.
No, you haven't.

Your timing diagram shows ONLY the clk and Y. It doesn't show the output of ANY of the four flip flops.

First, label all of the FF outputs. Since A and B are already used, let's call the others C and D.

Put all five of these signals on a timing diagram along with a sixth signal for the CLK.

Next, establish the starting condition that applies BEFORE the first transition of CLK. That means that C is set to 1 and A, B, and D are set to 0.

Now walk across the timing diagram and at each clock edge determine what changes happen to each signal.

Keep in mind that the changes to a FF output happen slightly AFTER the clock edge in such a way as to be too late to affect what happens to other flip flops on that same edge.

#### dl324

Joined Mar 30, 2015
15,511
That was my immediate thought, too. But look at the diagram.
I worked it out and the Y pulses don't behave the way the OP has shown.

#### WBahn

Joined Mar 31, 2012
28,185
I worked it out and the Y pulses don't behave the way the OP has shown.
Of that I have little doubt. But the circuit doesn't fundamentally preclude Y transitions on both clock edges (unless I'm missing something).

As to whether it actually DOES transition on both edges, I don't know, but I would expect it to be more likely to do so than not.

I haven't walked it through, but given that there is a single 1 going around the ring register and that other FF is a half-clock delay of the other signal driving the OR gate, I would expect Y to be pulses that are 1.5 clocks long.

I don't think that's giving too much away, particularly when it's little more than a WAG right now.

But, whatever mixture of edges one Y pulse is related to, I would expect (but don't think I can categorically say that it must be this way) the next Y pulse to be lined up the same way, which the waveform you were referring to wasn't.

#### Benengineer

Joined Feb 6, 2016
133
Of that I have little doubt. But the circuit doesn't fundamentally preclude Y transitions on both clock edges (unless I'm missing something).

As to whether it actually DOES transition on both edges, I don't know, but I would expect it to be more likely to do so than not.

I haven't walked it through, but given that there is a single 1 going around the ring register and that other FF is a half-clock delay of the other signal driving the OR gate, I would expect Y to be pulses that are 1.5 clocks long.

I don't think that's giving too much away, particularly when it's little more than a WAG right now.

But, whatever mixture of edges one Y pulse is related to, I would expect (but don't think I can categorically say that it must be this way) the next Y pulse to be lined up the same way, which the waveform you were referring to wasn't.
Thank you for your guys help. What is final answer for this questions?

#### dl324

Joined Mar 30, 2015
15,511
Thank you for your guys help. What is final answer for this questions?
Doesn't work that way.

You need to show your work and we'll try to guide you to the correct solution.

#### WBahn

Joined Mar 31, 2012
28,185
Thank you for your guys help. What is final answer for this questions?

It is YOUR homework. We will NOT just work it for you. We will help YOU work it.

#### Benengineer

Joined Feb 6, 2016
133

It is YOUR homework. We will NOT just work it for you. We will help YOU work it.
This is not homework, this is an interview questions. I still need to help with the questions.

#### WBahn

Joined Mar 31, 2012
28,185
This is not homework, this is an interview questions. I still need to help with the questions.
You've been given significant hints and suggestions and outright directions on how to approach it and you won't even try. In particular, you've been told to try to draw a timing diagram that includes all of the signals, which is at most sophomore level skill, and you won't even try. You just want someone to give you the answer.

Why should any company think that the effort you put forth for them will be any greater, particularly since the primary role of an engineer is solve problems for the people paying them?

#### dl324

Joined Mar 30, 2015
15,511
This is not homework, this is an interview questions.
You're playing semantics. This is work that you're expected to do on your own so the interviewer can find out what you know; not what we know.
I still need to help with the questions.
And if you'll show your work so we can see how you arrived at multiple incorrect answers, we can guide you to the correct solution.

We know how to do the problem and you don't. If we simply give you the answer, you won't know how to do it for similar problems in the future.

We're actually doing you a favor in teaching you how to solve the problem correctly. You're being short sighted in wanting instant gratification.

I solved this problem in order to be able to tell you that your answer was wrong. I've been waiting for you to show how you arrived at the wrong answer so I could point out where you're going wrong.

Last edited: