Digital Electronic - Can anyone design circuit ?

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Geeva

Joined Sep 19, 2017
3
AUTOMATIC DOOR BELL :

An automatic doorbell rings as soon as a person arrives at the door. The person who comes to the house need not search for the doorbell and press it any more. The circuit will automatically sense the presence of the person and it rings the doorbell.

D flip-flop: D flip-flop is an element which holds data in its internal storage and the output becomes equal to D, each time Clk enables the circuit (by changing to 1).

a) Logic table Clock D Q 0 X Memory state (no change) 0→1 0 0 0→1 1 1

T flip-flop: The flip-flop complements its output when the clock pulse occurs while the T input is 1.

a) Logic Table Clock T Q 0 X Memory state (Q) 0→1 0 Memory state (Q) 0→1 1 Complement of Q (Q’)

Clock signal can be generated using 555 Timer IC.

Binary Counter: A counter has a natural count of 2n , where ‘n’ is the flip-flops in the counter. In asynchronous counters, each flip-flop is triggered by the previous flip-flop. Here a 3-bit up counter is designed with three T Flip-flops. The counter is designed in such a way that, for each clock transition, the count gets incremented by one.
 

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GopherT

Joined Nov 23, 2012
8,012
AUTOMATIC DOOR BELL :

An automatic doorbell rings as soon as a person arrives at the door. The person who comes to the house need not search for the doorbell and press it any more. The circuit will automatically sense the presence of the person and it rings the doorbell.

D flip-flop: D flip-flop is an element which holds data in its internal storage and the output becomes equal to D, each time Clk enables the circuit (by changing to 1).

a) Logic table Clock D Q 0 X Memory state (no change) 0→1 0 0 0→1 1 1

T flip-flop: The flip-flop complements its output when the clock pulse occurs while the T input is 1.

a) Logic Table Clock T Q 0 X Memory state (Q) 0→1 0 Memory state (Q) 0→1 1 Complement of Q (Q’)

Clock signal can be generated using 555 Timer IC.

Binary Counter: A counter has a natural count of 2n , where ‘n’ is the flip-flops in the counter. In asynchronous counters, each flip-flop is triggered by the previous flip-flop. Here a 3-bit up counter is designed with three T Flip-flops. The counter is designed in such a way that, for each clock transition, the count gets incremented by one.
Yes, many people here can design such a circuit. What do you need exactly?

A schematic? A homework answer? A PCB design? A finished PCB? A Finished board with all components soldered in place?
 

philba

Joined Aug 17, 2017
960
Well, probably because it's not a schematic that contains complete information. Ignoring the lack of things like power connections, grounds and such, the counter isn't going to be driving a speaker. Plus, what is the sensor? I'd call it a conceptual diagram.
 
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