Hello, I am trying to build this circuit on a breadboard. I encountered a problem where the minute counter wont work if the first digit (M0) is 0. However, it counts normally from 1, 2, …, 9, 0 every time it finishes counting 60 seconds. Once it returns to 0, it wont count to 1. Is it possible that this is a problem with the current output of the 74ls08? I’ve checked the breadboard connections and tested the ICs separately. How can I fix this?

p.s. I used an Arduino as a voltage source and 1hz clock supply

 

A couple things come immediately to mind. First, you have a non-debounced switch contending with a logic gate output going to a clock input -- there's several kinds of bad in that.

Next, you are using gate logic to generate clock signals -- i.e., you have an asynchronous logic design. That means you are taking on the responsibility to fully analyze all timing parameters to ensure that all set-up and hold times are always satisfied and that it is impossible to have critical races or glitches at any time.

 

A couple things come immediately to mind. First, you have a non-debounced switch contending with a logic gate output going to a clock input -- there's several kinds of bad in that.

Next, you are using gate logic to generate clock signals -- i.e., you have an asynchronous logic design. That means you are taking on the responsibility to fully analyze all timing parameters to ensure that all set-up and hold times are always satisfied and that it is impossible to have critical races or glitches at any time.

I’ve read about switch debouncing, but I still lack the knowledge to design one. What I don’t know is how to choose the capacitor value, and what time period is enough to enable the TTL gate IC. Can you enlighten me about these?

As for your second note, would it be better to use a diode-equivalent circuit for an AND gate instead of 74ls08 (for less propagation delays)? I have little knowledge when it comes to the working principles of ICs as this is my first time building a personal project using actual components. I’ve only designed circuits using simulations.

 

From my observation, the 74ls08 doesn’t seem to work effectively. Sometimes the AND gates work, and sometimes it doesn’t. What could be the cause of its inefficiency?

 

I’ve read about switch debouncing, but I still lack the knowledge to design one. What I don’t know is how to choose the capacitor value, and what time period is enough to enable the TTL gate IC. Can you enlighten me about these?

A time constant of 50 ms to 200 ms usually works fine.

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As for your second note, would it be better to use a diode-equivalent circuit for an AND gate instead of 74ls08 (for less propagation delays)? I have little knowledge when it comes to the working principles of ICs as this is my first time building a personal project using actual components. I’ve only designed circuits using simulations.
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It would be better to design a fully-synchronous circuit unless you are willing to tackle the demons that lie in the home waters of asynchronous logic.

 

From my observation, the 74ls08 doesn’t seem to work effectively. Sometimes the AND gates work, and sometimes it doesn’t. What could be the cause of its inefficiency?

While I can't rule out a defective '08 chip, the problem is almost certainly not the chip, but the inputs to those chips owing to the asynchronous design.

 

It would be better to design a fully-synchronous circuit unless you are willing to tackle the demons that lie in the home waters of asynchronous logic.

If I were to redesign the circuit to make it fully-synchronous, would that mean a major change in the entirety of the design, or I'll just need to add flip flops for each 74ls93 clock input? Most of the digital clocks I saw on the web are designed this way, hence, I have no idea how to convert this into a fully-synchronous design.

 

If you want to design with ripple counters, use 74LS90 for decade counter and 74LS92 for divide-by-six counter.

 

Most of the digital clocks I saw on the web are designed this way

Did they all use the strange method you're using for resetting the counters? You've already used an AND gate to decode the clock to the next stage. Why not use that to also reset the counters?

FWIW, it looks like the circuit you have should work. But I haven't done a glitch analysis.

hence, I have no idea how to convert this into a fully-synchronous design.

Use commercial synchronous counters. It's more interesting to design your own counters, but that will take more IC's.

From my observation, the 74ls08 doesn’t seem to work effectively. Sometimes the AND gates work, and sometimes it doesn’t. What could be the cause of its inefficiency?

Could be a defective gate. Are these know to be good?